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intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet the intel ? ixf1110 is a 10-port ethernet media a ccess controller (mac) that supports ieee 802.3 1000 mbps applicatio ns. the device supports a system packet interface level 4 phase 2 (spi4-2) system interface to th e network processor or asic, and implements an internal serializer/deserializer (serdes) to allow direct connection to opti cal modules. the integration of the serdes functionality reduces pcb re al-estate and system-cost requirements. applications in general, the ixf1110 is appropriate for high-end switching applications where mac and serdes functions are not integrated into the system asic. product features high-end optical ethernet switches multi-service optical ethernet switches high-end ethernet lan/wan routers supports 10 independent 1000 mbps full- duplex ethernet mac ports system packet interface level 4 phase 2 (spi4-2) ? capable of data transfers from 10.24 gbps up to 12.8 gbps ? supports dynamic phase alignment ? integrated termination serdes interface with gbic for ethernet physical connectivity ? integrated termination ?i 2 c read/write capability 32-bit cpu interface rmon statistics jtag boundary scan capable compliance with ieee 802.3x standard for flow control jumbo frame support for 9.6 kb packets .18 cmos process technology supports ieee 802. 3 fiber auto- negotiation, including forced mode sff-8053, revision 5.5 compatible internal 17.0 kb receive fifo and 4.5 kb transmit fifo per channel independent enable/disable of any port detection of overly large packets error counters for dropped and errored packets crc calculation and error detection programmable option to: ? filter packets with errors ? filter, broadcast, multicast, and unicast address packets ? automatically pad transmitted packets less than the minimum frame size 552-ceramic ball grid array (cbga) 1.8 v and 2.5 v operation power consumption: 490 mw per-port typical document #: 250210 revision #: 004 rev. date: december 18, 2002 notice: this document contains preliminary informati on on new products. the specifications are subject to change without notice. veri fy with your local intel sales office that you have the latest datasheet before finalizing a design.
2 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property righ ts is granted by this document. except as provided in intel's terms and conditions of sale for such products, in tel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products includi ng liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining applications. intel may make changes to specifications and pr oduct descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instruct ions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. ixf1110 may contain design defects or errors know n as errata which may cause the product to deviate from published specifications. cur rent characterized errata are available on request. contact your local intel sales office or your distributor to obt ain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are refer enced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 2002 *third-party brands and names are the property of their respective owners.
contents preliminary datasheet 3 document #: 250210 revision #: 004 rev. date: december 18, 2002 contents 1.0 general description......................................................................................................... .13 2.0 pin assignments and signal descriptions.... .................................................................... 16 2.1 signal name conventions................................................................................... 16 2.2 power sequencing ..............................................................................................23 3.0 functional descriptions .................................................................................................... 2 5 3.1 media access controller ..................................................................................... 25 3.1.1 general description................................................................................ 25 3.1.2 mac functions....................................................................................... 25 3.1.2.1 padding of undersized frames on transmit ............................. 25 3.1.2.2 automatic crc generation ....................................................... 26 3.1.2.3 filtering of receive packets ...................................................... 26 3.1.2.4 pause command frames ....................................................... 28 3.1.3 fiber operation ...................................................................................... 28 3.1.4 auto-negotiation..................................................................................... 28 3.1.5 forced mode operation ......................................................................... 29 3.1.6 jumbo packet support ........................................................................... 29 3.1.7 rmon statistics support ....................................................................... 30 3.1.7.1 rmon statistics ........................................................................ 30 3.1.7.2 conventions .............................................................................. 32 3.1.7.3 ixf1110additional statistics...................................................... 32 3.1.8 transmit pause control interface........................................................... 33 3.2 system packet interface level 4 phase 2........................................................... 35 3.2.1 data path ............................................................................................... 35 3.2.1.1 control words ........................................................................... 36 3.2.1.2 dip4 .......................................................................................... 38 3.2.2 start-up parameters .............................................................................. 40 3.2.2.1 calendar_len ...................................................................... 40 3.2.2.2 calendar_m .......................................................................... 41 3.2.2.3 dip2_thr ................................................................................... 41 3.2.2.4 loss_of_sync ........................................................................... 41 3.2.2.5 data_max_t ........................................................................... 41 3.2.2.6 rep_t ....................................................................................... 41 3.2.2.7 dip4_unlock ............................................................................ 41 3.2.2.8 dip4_lock ................................................................................. 42 3.2.2.9 maxburst1 ................................................................................. 42 3.2.2.10maxburst2 ................................................................................. 42 3.2.3 training sequence for dynamic phase alignment (data path de-skew) ................................................................................................ 42 3.2.3.1 training at start-up.................................................................... 42 3.2.3.2 periodic training ....................................................................... 42 3.2.3.3 training in a practical implementation ...................................... 43 3.2.4 fifo status channel.............................................................................. 43 3.2.5 dc parameters....................................................................................... 47 3.3 serdes interface ................................................................................................. 47 3.3.1 introduction............................................................................................. 47 3.3.2 features ................................................................................................. 47
contents 4 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 3.3.3 functional description............................................................................ 48 3.3.3.1 transmitter operational overview............................................. 48 3.3.3.2 receiver operational overview................................................. 48 3.4 gigabit interface converter ................................................................................. 48 3.4.1 introduction ............................................................................................ 48 3.4.2 gbic description ................................................................................... 48 3.4.3 ixf1110 supported gbic interface signals .......................................... 49 3.4.4 functional descriptions .......................................................................... 50 3.4.4.1 high-speed serial interface ...................................................... 50 3.4.4.2 low-speed status signaling interface ...................................... 51 3.4.5 i 2 c module configuration interface ........................................................ 53 3.4.5.1 general description................................................................... 54 3.4.5.2 i 2 c protocol specifics................................................................ 56 3.4.5.3 port protocol operation............................................................. 57 3.4.5.4 clock and data transitions ....................................................... 57 3.4.5.5 ac timing characteristics......................................................... 60 3.5 led interface ...................................................................................................... 60 3.5.1 introduction ............................................................................................ 60 3.5.2 modes of operation................................................................................ 60 3.5.3 led interface signal description ........................................................... 61 3.5.4 mode 0: detailed operation ................................................................... 61 3.5.5 mode 1: detailed operation ................................................................... 62 3.5.6 power-on, reset, and initialization ........................................................ 63 3.5.7 led data decodes ................................................................................ 63 3.5.7.1 led signaling behavior ............................................................ 64 3.6 cpu interface...................................................................................................... 65 3.6.1 general description ............................................................................... 65 3.6.2 functional description............................................................................ 65 3.6.2.1 read access ............................................................................. 65 3.6.2.2 write access ............................................................................. 66 3.6.3 endian .................................................................................................... 67 3.7 clocks ................................................................................................................. 67 3.7.1 system interface reference clocks ....................................................... 67 3.7.1.1 clk125 ..................................................................................... 67 3.7.1.2 clk50 ....................................................................................... 67 3.7.2 spi4-2 receive and transmit data path clocks.................................... 67 3.7.3 jtag clock ............................................................................................ 68 3.7.4 gbic clock ............................................................................................ 68 3.7.5 led clock .............................................................................................. 68 4.0 applications................................................................................................................ ...... 69 4.1 tx and rx fifo operation................................................................................. 69 4.1.1 tx fifo ................................................................................................. 69 4.1.2 rx fifo ................................................................................................. 70 4.2 reset and initialization ........................................................................................ 70 4.3 optical module connections to the ixf1 110....................................................... 70 4.3.1 sfp-to-ixf1110 connection .................................................................. 70 4.3.2 sff-to-ixf1110 connection .................................................................. 73 4.3.3 1 x 9-to-ixf1110 connection ................................................................. 75
contents preliminary datasheet 5 document #: 250210 revision #: 004 rev. date: december 18, 2002 5.0 test specifications ......................................................................................................... ..77 6.0 register definitions ........................................................................................................ .. 92 6.1 introduction.......................................................................................................... 92 6.2 document structure ............................................................................................ 92 6.3 graphical representation....................... ............................................................. 92 6.4 per port registers ............................................................................................... 94 6.5 memory map ....................................................................................................... 95 6.5.1 mac control registers.........................................................................102 6.5.2 mac rx statistics register overview..................................................110 6.5.3 mac tx statistics register overview ..................................................114 6.5.4 global status and configuration register overview ............................118 6.5.5 global rx block register overview.....................................................123 6.5.6 tx block register overview.................................................................131 6.5.7 spi4-2 block register overview ..........................................................140 6.5.8 serdes register overview ...................................................................142 6.5.9 gbic block register overview ............................................................144 7.0 package overview .........................................................................................................147 7.1 features ............................................................................................................147 7.2 package specifics for the ixf1110 ...................................................................147 7.2.1 markings...............................................................................................148 8.0 product ordering informatio n .........................................................................................151 figures 1 ixf1110 block diagram ...................................................................................... 13 2 intel ? ixf1110 system block dia gram ............................................................... 14 3 ixf1110 552-ball cbga assignments (t op view) ............................................ 15 4 ixf1110 pinout diagram .................................................................................... 16 5 power sequencing diagram................................................................................ 23 6 transmit pause control interface........................................................................ 34 7 ixf1110 spi4-2 interfacing with the network processor or forwarding engine.35 8 data path state diagram ................................................................................... 36 9 per-port state diagram with transitions at control words ................................ 38 10 dip-4 calculation boundaries ................ ............................................................. 39 11 dip-4 calculation algorithm ................................................................................ 40 12 fifo status state diagram ................................................................................ 44 13 example of dip-2 encoding ............................................................................... 45 14 typical gbic module functional diagram ......................................................... 49 15 data path connection and termination . ............................................................. 51 16 data validity timing diagram.............................................................................. 57 17 start and stop definition timing diagram ........................................................... 57 18 acknowledge timing diagram ............................................................................ 58 19 random read .................................................................................................... 59 20 byte write............................................................................................................ 60 21 mode 0 timing diagram ..................................................................................... 61 22 mode 1 timing diagram ..................................................................................... 63 23 read timing diagram - asynchronous interface ............................................... 66 24 write timing diagram - asynchronous interface ................................................ 66
contents 6 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 25 packet buffering fifo......................................................................................... 69 26 sfp-to-ixf1110 connection diagram ......... ....................................................... 71 27 sff-to-ixf1110 connection diagram................................................................. 73 28 1 x 9-to-ixf1110 connection .............................................................................. 75 29 cpu port read timing diagram ........... ............................................................. 80 30 cpu port write timing diagram ........................................................................ 80 31 jtag timing diagram......................................................................................... 82 32 transmit pause control interface diagram ......................................................... 83 33 gbic interrupt timing ............................ ............................................................. 84 34 hardware reset timing diagram ........................................................................ 84 35 led timing diagram ........................................................................................... 85 36 serdes timing diagram ...................................................................................... 86 37 spi4-2 transmit fifo status bus timing diagram ............................................ 88 38 spi4-2 receive fifo status bus timing diagram ............................................. 89 39 i 2 c bus timing diagram ..................................................................................... 90 40 i 2 c write cycle diagram .................................................................................... 90 41 memory overview diagram ................................................................................ 93 42 register overview diagram ............................................................................... 94 43 ixf1110 552-ceramic ball gr id array (cbga) package specification............. 149 44 ixf1110 cbga package side view diagram ................................................... 150 45 ordering information - sample .......................................................................... 151 tables 1 ixf1110 signal pins............................................................................................ 17 2 ixf1110 power supply signal descriptions........................................................ 22 3 ixf1110 unused balls/reserved ........................................................................ 23 4 power sequencing .............................................................................................. 24 5 pause packets drop enable behavior ................................................................ 27 6 crc errored packets drop enable behavior ..................................................... 27 7 rmon additional statistics registers ................................................................. 31 8 valid decodes for txpausea dd[3:0] ................................................................... 33 9 control word format........................................................................................... 37 10 control word definitions ..................................................................................... 37 11 fifo status format ............................................................................................ 46 12 ixf1110-to-gbic connections ........................................................................... 49 13 led pin descriptions .......................................................................................... 61 14 mode 0 clock cycle to da ta bit relationship...................................................... 62 15 mode 1 clock cycle to da ta bit relationship...................................................... 63 16 led data decodes ............................................................................................. 64 17 ixf1110 led behavior ....................................................................................... 65 18 sfp-to-ixf1110 connection ............................................................................... 71 19 sff-to-ixf1110 connection ............................................................................... 73 20 1 x 9-to-ixf1110 connection .............................................................................. 75 21 absolute maximum ratings ................... ............................................................. 77 22 operating conditions ......................................................................................... 78 23 2.5 v lvttl and cmos i/o electrical characteristics ....................................... 78 24 lvds i/o electrical characteristics..................................................................... 78 25 cpu timing parameters ..................................................................................... 80 26 jtag timing parameters.................................................................................... 82 27 transmit pause control interface parame ters .................................................... 83
contents preliminary datasheet 7 document #: 250210 revision #: 004 rev. date: december 18, 2002 28 gbic interrupt timing para meters...................................................................... 84 29 hardware reset timing pa rameters ................................................................... 84 30 led timing parameters ............................ .......................................................... 85 31 transmitter characteristics .................... ............................................................. 86 32 receiver characteristics ..................................................................................... 87 33 spi4-2 transmit fifo status bus timing parameters ....................................... 88 34 spi4-2 receive fifo status bus timing parameters ........................................ 89 35 i 2 c ac timing characteristics............................................................................. 90 36 mac control register map ................................................................................. 95 37 mac rx statistics register map......................................................................... 96 38 mac tx statistics register map ......................................................................... 97 39 global status and configuration register map ................................................... 97 40 rx block register map ....................................................................................... 98 41 tx block register map........................................................................................ 99 42 spi4-2 block register map ...............................................................................100 43 serdes block register map ..............................................................................101 44 gbic block register map ...................... ...........................................................101 45 station address register low (addr: port_index + 0x00).................................102 46 station address register high (addr: port_index + 0x01) ................................102 47 fdfc type register (addr: port_index + 0x03) ...............................................102 48 fc tx timer value register (addr: port_index + 0x07) ...................................102 49 fdfc address low register (addr: port_index + 0x08) ..................................103 50 fdfc address high register (addr: port_index + 0x09) .................................103 51 ipg transmit time register (addr: port_index + 0x0c) ...................................103 52 pause threshold register (addr: port_index + 0x0e) ......................................103 53 max frame size register (addr: port_ind ex + 0x0f) .......................................104 54 fc enable register (addr: port_index + 0x12).................................................104 55 short runts threshold register (addr: po rt_index + 0x14)..............................104 56 discard unknown control frame register (addr: port_index + 0x15)..............104 57 rx config word register (addr: port_index + 0x16)........................................105 58 tx config word register (addr: port_index + 0x17) ........................................106 59 diverse config register (addr: port_index + 0x18) ..........................................106 60 rx packet filter control register (add r: port_index + 0x19) ...........................107 62 port multicast address high register (addr: port_index + 0x1b) .....................109 61 port multicast address low register (addr: port_index + 0x1a)......................109 63 mac rx statistics registers (addr: port_index + 0x20 - port_index + 0x39) ..110 64 mac tx statistics registers (addr: port _index + 0x40 - port _index + 0x58) ..114 65 port enable register (addr: 0x500) ..................................................................118 66 link led enable register (addr: 0x502) ..........................................................119 67 cpu interface register (addr: 0x508)...............................................................120 68 led control register (addr: 0x509)..................................................................120 69 led flash rate register (addr: 0x50a) ...........................................................120 70 led fault disable register (addr: 0x50b)........................................................121 71 jtag id revision register (addr: 0x 50c) ........................................................122 72 rx fifo high watermark ports 0 to 9 re gisters (addr: 0x580 - 0x589)..........123 73 rx fifo low watermark ports 0 to 9 re gisters (addr: 0x58a - 0x593) ..........124 74 rx fifo number of frames removed ports 0 to 9 registers (addr: 0x594 - 0x59d) .......................................................................................126 75 rx fifo errored frame drop enable regi ster (addr: 0x59f) .........................128 76 rx fifo overflow event register (addr: 0x5a0) .............................................129
contents 8 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 77 tx fifo high watermark ports 0 to 9 (a ddr: 0x600 - 0x609) .......................... 131 78 tx fifo low watermark ports 0 to 9 (a ddr: 0x60a - 0x613)........................... 132 79 tx fifo mac transfer threshold ports 0 to 9 (addr: 0x614 - 0x61d) ............ 134 80 tx fifo overflow event register (addr: 0x61e) ............................................. 137 81 tx fifo info out-of-sequence register (addr: 0x621) .................................... 138 82 tx fifo number of frames removed po rts 0-9 (addr: 0x622 - 0x62b) ......... 139 83 spi4-2 rx burst size register (addr: 0x700)................................................... 140 84 spi4-2 rx training register (addr: 0x 701) ...................................................... 140 85 spi4-2 rx calendar register (addr: 0x702) .................................................... 141 86 spi4-2 tx synchronization register (addr: 0x703) .......................................... 142 87 tx and rx ac/dc coupling selection register (addr: 0x780) ........................ 142 88 tx and rx power-down ports 0-9 regist er (addr: 0x787) ............................... 143 89 rx signal detect level ports 0-9 register (addr: 0x793) ................................. 143 90 gbic status register ports 0-9 (addr: 0x799) ................................................. 144 91 gbic control register ports 0-9 regist er (addr: 0x79a) ................................. 144 92 i 2 c control register ports 9-0 register (addr: 0x79b) ..................................... 145 93 i 2 c data register ports 9-0 register (addr: 0x79c)......................................... 146 94 product information ........................................................................................... 151
contents preliminary datasheet 9 document #: 250210 revision #: 004 rev. date: december 18, 2002 revision history revision: 004 revision date: december 6, 2002 page # description 1 modified first paragraph modified first line under applications. added text under product features on title page. 23 modified figure 5 ?power sequencing diagram? 25 modified third bullet and last paragraph under section 3.1.1, ?general description? . 25 changed heading from ?features? to section 3.1.2, ?mac functions? . 26 modified section 3.1.2.3.1, ?filter on unicast packet match? , section 3.1.2.3.2, ?filter on multicast packet match? , section 3.1.2.3.3, ?filter broadcast packets? . 28 modified text under section 3.1.3, ?fiber operation? . 28 modified text under section 3.1.4, ?auto-negotiation? . 29 added section 3.1.5, ?forced mode operation? . 32 changed heading from ixf1110 advantages to section 3.1.7.3, ?additional statistics? . n/a deleted old table 9: interface timing 41 modified section 3.2.2.7, ?dip4_unlock? and section 3.2.2.8, ?dip4_lock? . 42 modified section 3.2.2.10, ?maxburst2? (maxburst1 to maxburst2). 53 modified section 3.4.5, ?i 2 c module configuration interface? (read only to read/write capable). 53 section 3.4.5.1.2, ?write access operation example? : changed read to write for item numbers 4 and 5; modified note. 59 modified section 3.4.5.4.6, ?random read operation? 59 added section 3.4.5.4.7, ?byte write operation? . 68 modified section 3.7.5, ?led clock? : changed 500 mhz to 720 mhz. 70 modified section 4.2, ?reset and initialization? : changed 220 us to 4.11 ms in third paragraph. 84 modified table 29 ?hardware reset timing parameters? : changed min value for reset recovery time. 88 modified figure 37 ?spi4-2 transmit fifo status bus timing diagram? and table 33 ?spi4-2 transmit fifo status bus timing parameters? : modified parameters. 89 modified figure 38 ?spi4-2 receive fifo status bus timing diagram? and table 34 ?spi4-2 receive fifo status bus timing parameters? : modified parameters. 97 added jtag register to table 39 ?global status and configuration register map? . 110 modified rxsymbolerrors description in table 63 ?mac rx statistics registers (addr: port_index + 0x20 - port_index + 0x39)? . 101 modified table 44 ?gbic block register map? . 110 added notes to rxrunterrors and rxshorterrors description in table 63 ?mac rx statistics registers (addr: port_index + 0x20 - port_index + 0x39)? (fiber only). 120 modified table 69 ?led flash rate register (addr: 0x50a)? . 122 added table 71 ?jtag id revision register (addr: 0x50c)? . 134 changed default value in table 79 ?tx fifo mac transfer threshold ports 0 to 9 (addr: 0x614 - 0x61d)? . 141 modified bits 12 and 28 descriptions in table 85 ?spi4-2 rx calendar register (addr: 0x702)?
contents 10 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 142 changed default value for bits 15:8 in table 86 ?spi4-2 tx synchronization register (addr: 0x703)? . 145 modified into two tables: table 92 ?i 2 c control register ports 9-0 register (addr: 0x79b)? and table 93 ?i 2 c data register ports 9-0 register (addr: 0x79c)? 148 added marking diagram under section 7.2.1, ?markings? . revision: 004 revision date: december 6, 2002 page # description revision: 003 revision date: october 7, 2002 page # description 1 modified product features on front page: added ?integrated termination? under spi4-2 interface 1 added ?integrated termination? under serdes interface 23 added new section: section 2.2, ?power sequencing? including figure 5 ?power sequencing diagram? and table 4 ?power sequencing? . 26 added note under section 3.1.2.3, ?filtering of receive packets? regarding jumbo frames. 28 modified text under section 3.1.4, ?auto-negotiation? . 29 modified text under section 3.1.6, ?jumbo packet support? . 31 modified table 7 ?rmon additional statistics registers? . 36 added new section: section 3.2.1.1, ?control words? , including table 9 ?control word format? and table 10 ?control word definitions? . 38 added new section: section 3.2.1.2, ?dip4? . 44 modified figure 12 ?fifo status state diagram? . 48 modified second paragraph under section 3.3.3.1, ?transmitter operational overview? . 66 updated table 23 ?read timing diagram - asynchronous interface? and table 24 ?write timing diagram - asynchronous interface? . 67 added bullet to section 3.7.2, ?spi4-2 receive and transmit data path clocks? : ?tsclk frequency is 1/4 tdclk frequency.? 70 removed second ?note? under section 4.2, ?reset and initialization? . 70 added new section section 4.3, ?optical modul e connections to the ixf1110? including: table 18 ?sfp-to-ixf1110 connection? and figure 26 ?sfp-to-ixf1110 connection diagram? ; table 19 ?sff-to-ixf1110 connection? and figure 27 ?sff-to-ixf1110 connection diagram? ; table 20 ?1 x 9-to-ixf1110 connection? and figure 28 ?1 x 9-to-ixf1110 connection? . 78 added note 2 to table 23 ?2.5 v lvttl and cmos i/o electrical characteristics? . 84 modified table 29 ?hardware reset timing parameters? : min value of reset recovery time. 84 modified table 29 ?hardware reset timing parameters? : reset pulse wide min = 100 ns. reset recovery time min = 220 s. 86 / 87 modified table 31 ?transmitter characteristics? and table 32 ?receiver characteristics? . added introductory text. 97 modified table 39 ?global status and configuration register map? . 94 added text to bits 9:0 description under tabl e 50 ? ?specified in multiples of 512 bit times.
contents preliminary datasheet 11 document #: 250210 revision #: 004 rev. date: december 18, 2002 94 added text to bits 9:0 description under tabl e 51 ? ?specified in multiples of 512 bit times. 103 added text to bits 9:0 description under table 51 ?ipg transmit time register (addr: port_index + 0x0c)? ? ?specified in multiples of 512 bit times. 103 added text to bits 15:0 description under table 52 ?pause threshold regi ster (addr: port_index + 0x0e)? ? ?specified in multiples of 512 bit times. 105 changed subclause number for register description under table 57 ?rx config word register (addr: port_index + 0x16)? . bits 13:12: added to bit description. changed default values for bits 8:5. 106 modified table 59 ?diverse config register (addr: port_index + 0x18)? ? bits 15:9, 8, 4:0 are now reserved. modified bit 5 name and description; added ?1 = normal operation.? added note. 107 added ?table note 3? to table 60 ?rx packet filter control register (addr: port_index + 0x19)? . 114 table 64 ?mac tx statistics registers (addr: port_index + 0x40 - port_index + 0x58)? : changed ?txoctetstransmittedok? to ?txoctetstotalok?. txpkts1519tomaxoctets: changed 1526 to 1523. 118 modified register description under table 65 ?port enable register (addr: 0x500)? : change ?setting the bit to 0 de-asserts the reset.? to ?setting the bit to 0 disables the port.? 120 modified table 68 ?led control register (addr: 0x509)? : bit 0: changed ?led control? to ?led_sel_mode?. 140 modified bit 31 description under table 83 ?spi4-2 rx burst size register (addr: 0x700)? . 141 modified table 85 ?spi4-2 rx calendar register (addr: 0x702)? : modified descriptions for bits 19:16, 11:8, and 3:0. 142 modified table 86 ?spi4-2 tx synchroniz ation register (addr: 0x703)? : added new description for bits 7:4. revision: 002 revision date: july 2002 page # description 20 modified figure 8 ?ixf1110 552-ball cbga assignments (top view)?. 22 modified table 1 ?ixf1010/ixf1110 signal pins?. 31 modified table 3 ?ixf1110 powe r supply signal descriptions?. 28 added section 3.1.4, ?jumbo packet support?. 30 replaced section 3.1.5, ?rmon statistics support?. 46 added figure 12 ?ixf1010/ixf1110 spi4-2 interfacing with the network processor or forwarding engine?. 62 modified sections under section 3.7, ?clocks?. 66 added section 4.3, ?extras and back up?. 89 modified all register maps under section 6.5, ?memory map?. revision: 003 revision date: october 7, 2002 page # description
contents 12 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 related documents title order ixf1010 and ixf1110 10-port gigabit ethernet media access controllers design and layout guide 250676 ixf1110 demo board development kit manual 250807 spi4 phase 2 performance in gigabit ethernet me dia access controllers application note 250643 interfacing with ixf1010 and ixf1110 10-port gigabit ethernet media access controllers application note 250856 ixf1110 thermal design considerations application note 250289 flow control in ixf1010 and ixf1110 10-port gigabit ethernet media access controllers application note 250236
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 13 document #: 250210 revision #: 004 rev. date: december 18, 2002 1.0 general description the intel ? ixf1110 is a 10-port 1000 mbps ethe rnet media access controller (mac). the 10 gigabit interface to the network processor is supporte d through a system packet interface level 4 phase 2 (spi4-2), while the media interface is an integrated serializer /deserializer (serdes). figure 1 illustrates the ixf1110 block diagram and figure 2 represents the ixf1110 system block diagram. figure 1. ixf1110 block diagram spi4-2 spi4-2 scheduler cpu interface led controller rmon statistics gbic controller ixf1110 serdes 0 serdes 1 serdes 2 serdes 3 serdes 4 serdes 5 serdes 6 serdes 7 serdes 8 serdes 9 mac core rx/tx fifos 0 mac core rx/tx fifos 1 mac core rx/tx fifos 2 mac core rx/tx fifos 3 mac core rx/tx fifos 4 mac core rx/tx fifos 5 mac core rx/tx fifos 6 mac core rx/tx fifos 7 mac core rx/tx fifos 8 mac core rx/tx fifos 9
intel ? ixf1110 10-port gigabit ethernet media access controller 14 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 figure 2. intel ? ixf1110 system block diagram ixf1110 cpu led serial-to-parallel converter up if led serial interface port 0 optics module port 1 optics module port 2 optics module port 3 optics module port 4 optics module port 5 optics module port 6 optics module port 7 optics module port 8 optics module port 9 optics module serdes/gbic interface forwarding engine network processor spi4-2
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 15 document #: 250210 revision #: 004 rev. date: december 18, 2002 figure 3 provides the physical layout of the balls, labeled with their ball number (matrix layout) and signal name. figure 3. ixf1110 552-ball cb ga assignments (top view) 17 18 19 21 22 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 24 no pad no ball no ball upx_data1 n/c n/c upx_data3 upx_data7 upx_data9 upx_data8 upx_data 11 upx_data 19 rdat12+ rdat12- upx_data 20 upx_data 25 upx_data 27 upx_wr led_clk led_data upx_data 29 no ball no ball no ball a a no ball no ball upx_data0 vdd2 tdat2+ gnd tdat9+ vdd2 upx_data2 gnd tx_fault _int vdd2 vdd2 rx_los_ int gnd upx_data 22 vdd2 upx_data 28 gnd rdat1+ vdd2 upx_data 30 no ball no ball b b no ball upx_add 10 upx_add7 gnd tdat2- tdat7- tdat7+ tdat9- tdat14+ n/c tsclk upx_data4 upx_data6 upx_data 17 n/c rdat8+ upx_data 26 rdclk+ rdclk- rdat1- clk50 upx_rdy upx_data 31 no ball c c avdd vdd2 tdclk+ gnd gnd vdd upx_data 15 gnd tdat14- vdd vdd gnd gnd upx_data 16 vdd rdat8- gnd rdat9+ vdd vdd gnd gnd vdd2 gnd d d gnd upx_add5 upx_add4 tdclk- tstat0 tstat1 tdat11- tdat11+ tdat10+ upx_data 13 upx_data5 upx_data 10 rdat13+ rdat13- upx_data 23 rdat6+ rdat6- rdat9- rdat0+ rdat0- vdd i 2 c_data7 i 2 c_data4 avdd e e upx_add9 gnd upx_add2 vdd upx_add8 gnd tdat4+ vdd2 tdat10- gnd upx_data 14 vdd2 vdd2 upx_data 18 gnd rdat14+ vdd2 rdat2+ gnd upx_cs vdd i 2 c_data3 gnd i 2 c_data9 f f upx_add6 txpause add1 txpause add0 upx_add1 tdat5+ tdat4- n/c n/c tdat3+ gnd tdat15+ upx_data 12 upx_data 21 upx_data 24 mod_def _int rdat14- rdat10+ rdat10- rdat2- i 2 c_data6 rdat3+ i 2 c_data0 i 2 c_data1 i 2 c_data8 g g upx_add3 vdd2 tdat1+ gnd tdat5- vdd2 tdat12+ gnd tdat3- vdd tdat15- gnd gnd upx_rd vdd rctl+ gnd rctl- vdd2 rdat3- gnd n/c vdd2 i 2 c_data5 h h upx_add0 txpause add2 tdat1- vdd tdat0- tdat0+ txpausefr tdat12- tdat13+ gnd vdd vdd2 vdd2 vdd gnd rdat11+ rsclk rdat4+ rdat4- rstat1 gnd n/c gnd i 2 c_data2 j j txpause add3 gnd vdd vdd vdd gnd n/c vdd gnd tdat13- gnd rdat15+ rdat15- gnd rdat11- gnd vdd led_ latch gnd gnd vdd tx_ disable_ 0 gnd gnd k k mod_def _9 tx_fault _9 gnd tx_ disable_ 9 tdat8+ gnd tdat6- tdat6+ vdd gnd vdd gnd gnd vdd gnd vdd rdat5+ rdat5- i 2 c_clk rstat0 n/c rx_los_0 n/c gnd l l n/c vdd2 gnd gnd tdat8- vdd2 n/c gnd vdd2 tctl+ gnd vdd2 vdd2 gnd rdat7+ vdd2 gnd gnd vdd2 mod_def _3 gnd tx_ disable_ 1 vdd2 tx_ fault_0 m m n/c vdd2 avdd2 gnd n/c vdd2 n/c gnd vdd2 tctl- gnd vdd2 vdd2 gnd rdat7- vdd2 gnd trst vdd2 n/c gnd avdd2 vdd2 mod_def _0 n n gnd rx_los_9 avdd2 n/c n/c n/c avdd tx_fault -8 vdd gnd vdd gnd gnd vdd gnd vdd n/c avdd n/c n/c gnd avdd2 gnd gnd p p gnd gnd gnd vdd n/c gnd mod_def _8 vdd gnd gnd gnd rx_los_3 n/c gnd tx_fault _3 gnd vdd n/c gnd n/c vdd n/c gnd gnd r r n/c rx_los_8 tx_8+ mod_def _6 tx_9+ n/c gnd gnd gnd gnd vdd vdd2 vdd2 vdd gnd tms gnd gnd gnd rx_1+ gnd rx_0+ gnd rx_2- t t n/c vdd2 tx_8- gnd tx_9- vdd2 gnd gnd tx disable_ 6 vdd mod_def _5 gnd gnd tx_ disable_ 4 vdd gnd gnd tx_ disable_ 3 vdd2 rx_1- gnd rx_0- vdd2 rx_2+ u u n/c gnd gnd rx_8- rx_8+ avdd tx_ disable_ 8 n/c n/c avdd2 avdd rx_los_5 gnd avdd avdd2 gnd rx_los_1 avdd n/c tx_0+ tx_0- tx_2+ tx_fault _1 rx_3- v v n/c gnd gnd vdd gnd gnd gnd vdd2 tx_fault _6 gnd tx_fault _5 vdd2 vdd2 tx_fault _4 gnd n/c vdd2 n/c gnd gnd vdd tx_2- gnd rx_3+ w w avdd2 gnd gnd sys_res rx_9- rx_9+ n/c gnd rx_los_6 n/c n/c gnd gnd n/c gnd gnd tx_fault _2 gnd tx_1+ tx_1- mod_def _1 tx_3- tx_3+ tdo y y gnd vdd2 gnd gnd clk 125 vdd gnd gnd tx_ disable_ 7 vdd n/c gnd gnd gnd vdd mod_def _2 gnd tx_ disable_ 5 vdd n/c gnd n/c vdd2 tclk aa aa no ball mod_def _7 n/c vdd n/c gnd gnd n/c tx_6+ gnd tx_4- tx_4+ rx_4+ rx_4- rx_los_4 rx_6+ gnd n/c n/c n/c gnd n/c gnd no ball ab ab no ball no ball rx_los_7 vdd2 tx_fault _7 gnd gnd vdd2 tx_6- gnd gnd vdd2 vdd2 mod_def _4 gnd rx_6- vdd2 tdi gnd gnd vdd2 tx_ disable_ 2 no ball no ball ac ac no ball no ball no ball n/c n/c n/c n/c n/c tx_7+ tx_7- tx_5- tx_5+ rx_5+ rx_5- rx_7- rx_7+ n/c rx_los_2 n/c n/c gnd no ball no ball no ball ad ad 17 18 19 21 22 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 24
intel ? ixf1110 10-port gigabit ethernet media access controller 16 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 2.0 pin assignments and signal descriptions figure 4 and table 1 through table 3 on page 23 provide the signal pins used by the ixf1110 2.1 signal name conventions signal names may contain either a port design ation (media interface) or a serial designation (system interface). signal naming conventions are as follows: port designation . individual signals that apply to a partic ular port are designat ed by the signal mnemonic, immediately followed by an underscore an d the port designation. for example, gbic serial data signals would be identified as i 2 c_data_0, i 2 c_data_1, etc. serial designation. a set of signals that are not tied to any specific po rt are designated by the signal mnemonic, followed by a br acketed serial designation. for example, spi4-2 transmit data bus signals would be identified as tdat[15:0]. figure 4. ixf1110 pinout diagram ixf1110 tdat[15:0]+/- tdo rsclk rctl+/- rdclk+/- rstat[1:0] rdat[15:0]+/- tsclk tctl+/- tdclk+/- tstat[1:0] upx_add[10:0] upx_data[31:0] txpausefr txpauseadd[3:0] tclk tdi tms upx_wr upx_rd upx_cs upx_rdy serdes interface jtag interface cpu interface rx_9:0+/- spi4-2 interface tx_9:0+/- pause control interface gbic interface mod_def_9:0 tx_disable_9:0 tx_fault_9:0 rx_los_9:0 tx_fault_int rx_los_int mod_def_int i 2 c_clk i 2 c_data_9:0 led interface led_clk led_latch led_data clk125 system interface clk50 sys_res trst
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 17 document #: 250210 revision #: 004 rev. date: december 18, 2002 table 1. ixf1110 signal pins ball designator signal name type standard signal description spi4-2 interface g11, h11 c9, d9 j9, k10 h7, j8 e8, e7 e9, f9 b7, c8 l5, m5 c7, c6 l8, l7 g5, h5 f7, g6 g9, h9 b5, c5 h3, j3 j6, j5 tdat15+/- tdat14+/- tdat13+/- tdat12+/- tdat11+/- tdat10+/- tdat9+/- tdat8+/- tdat7+/- tdat6+/- tdat5+/- tdat4+/- tdat3+/- tdat2+/- tdat1+/- tdat0+/- input lvds transmit data bus: carries payload data and in-band control words to the ixf1110 link-layer device. internally terminated differentially with 100 ?. d3, e4 tdclk+, tdclk- input lvds transmit data clock: clock associated with tdat[15:0] and tctl. data and control lines are driven off the rising and falling edges of the clock. internally terminated differentially with 100 ?. m10, n10 tctl+, tctl- input lvds transmit control: tctl is high when a control word is present on tdat[15:0]. otherwise, tctl is low. internally terminated differentially with 100 ?. c11 tsclk output 2.5 v lvttl transmit status clock: clock associated with tstat [1:0]. frequency is equal to one- quarter tdclk. e6, e5 tstat1, tstat0 output 2.5 v lvttl transmit fifo status: carries round-robin fifo status information, along with associated error detection and framing. k12, k13 f16, g16 e13, e14 a13, a14 j16, k15 g17, g18 d18, e18 c16, d16 m15, n15 e16, e17 l17, l18 j18, j19 g21, h20 f18, g19 b20, c20 e19, e20 rdat15+/- rdat14+/- rdat13+/- rdat12+/- rdat11+/- rdat10+/- rdat9+/- rdat8+/- rdat7+/- rdat6+/- rdat5+/- rdat4+/- rdat3+/- rdat2+/- rdat1+/- rdat0+/- output lvds receive data: carries payload data and in-band control from the ixf1110 link-layer device.
intel ? ixf1110 10-port gigabit ethernet media access controller 18 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 c18, c19 rdclk+, rdclk- output lvds receive data clock: clock associated with rdat[15:0] and rctl. data and control lines are driven off the rising and falling edges of the clock. h16, h18 rctl+, rctl- output lvds receive control: rctl is high when a control word is present on rdat[15:0]. otherwise, rctl is low. j17 rsclk input 2.5 v lvttl receive status clock: clock associated with rstat[1:0]. j20, l20 rstat1, rstat0 input 2.5 v lvttl receive fifo status: carries round-robin fifo status information, along with associated error detection and framing. serdes interface t5, u5 t3, u3 ad9, ad10 ab9, ac9 ad12, ad11 ab12, ab11 y23, y22 v22, w22 y19, y20 v20, v21 tx_9+/- tx_8+/- tx_7+/- tx_6+/- tx_5+/- tx_4+/- tx_3+/- tx_2+/- tx_1+/- tx_0+/- output lv pecl transmit differential output: carries the 1.25 ghz data to the optics module. these lines can be ac- or dc- coupled. by default, these lines are ac-coupled internally. this can be changed (see table 87, ?tx and rx ac/dc coupling selection register (addr: 0x780)? on page 142 ). y6, y5 v5, v4 ad16, ad15 ab16, ac16 ad13, ad14 ab13, ab14 w24, v24 u24, t24 t20, u20 t22, u22 rx_9+/- rx_8+/- rx_7+/- rx_6+/- rx_5+/- rx_4+/- rx_3+/- rx_2+/- rx_1+/- rx_0+/- input lv pecl receive differential input: carries the 1.25 ghz data from the optics module. internally terminated differentially with 100 ? . these lines can be ac- or dc- coupled. by default, these lines are ac-coupled internally. this can be changed (see table 87, ?tx and rx ac/dc coupling selection register (addr: 0x780)? on page 142 ). cpu interface c2 f1 f5 c3 g1 e2 e3 h1 f3 g4 j1 upx_add10 upx_add9 upx_add8 upx_add7 upx_add6 upx_add5 upx_add4 upx_add3 upx_add2 upx_add1 upx_add0 input 2.5 v cmos address bus: 11-bit address bus f20 upx_cs input 2.5 v cmos chip select signal: active low chip select table 1. ixf1110 si gnal pins (continued) ball designator signal name type standard signal description
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 19 document #: 250210 revision #: 004 rev. date: december 18, 2002 c23 b22 a21 b18 a17 c17 a16 g14 e15 b16 g13 a15 a12 f14 c14 d14 d7 f11 e10 g12 a11 e12 a9 a10 a8 c13 e11 c12 a7 b9 a4 b3 upx_data31 upx_data30 upx_data29 upx_data28 upx_data27 upx_data26 upx_data25 upx_data24 upx_data23 upx_data22 upx_data21 upx_data20 upx_data19 upx_data18 upx_data17 upx_data16 upx_data15 upx_data14 upx_data13 upx_data12 upx_data11 upx_data10 upx_data9 upx_data8 upx_data7 upx_data6 upx_data5 upx_data4 upx_data3 upx_data2 upx_data1 upx_data0 input/ output 2.5 v cmos bi-directional data bus: 32-bit bi-directional data bus a18 upx_wr input 2.5 v cmos write strobe: active low write strobe h14 upx_rd input 2.5 v cmos read strobe: active low read strobe c22 upx_rdy open drain output 2.5 v cmos cycle complete indicator: indicates that read or write is complete pause control interface j7 txpausefr input 2.5 v cmos pause strobe: indicates when a pause frame is to be sent k1 j2 g2 g3 txpauseadd3 txpauseadd2 txpauseadd1 txpauseadd0 input 2.5 v cmos pause address bus: selects the port for the pause frames gbic interface l2 p8 ac5 w9 w11 w14 r15 y17 v23 m24 tx_fault_9 tx_fault_8 tx_fault_7 tx_fault_6 tx_fault_5 tx_fault_4 tx_fault_3 tx_fault_2 tx_fault_1 tx_fault_0 input 2.5 v cmos transmitter fault: input used to determine when there is a gbic transmitter fault. table 1. ixf1110 signal pins (continued) ball designator signal name type standard signal description
intel ? ixf1110 10-port gigabit ethernet media access controller 20 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 p2 t2 ac3 y9 v12 ab15 r12 ad18 v17 l22 rx_los_9 rx_los_8 rx_los_7 rx_los_6 rx_los_5 rx_los_4 rx_los_3 rx_los_2 rx_los_1 rx_los_0 input 2.5 v cmos receiver loss of signal: input used to determine when the gbic receiver loses synchronization. l1 r7 ab2 t4 u11 ac14 m20 aa16 y21 n24 mod_def_9 mod_def_8 mod_def_7 mod_def_6 mod_def_5 mod_def_4 mod_def_3 mod_def_2 mod_def_1 mod_def_0 input 2.5 v cmos module definition: input used to determine when a gbic module is present. l4 v7 aa9 u9 aa18 u14 u18 ac22 m22 k22 tx_disable_9 tx_disable_8 tx_disable_7 tx_disable_6 tx_disable_5 tx_disable_4 tx_disable_3 tx_disable_2 tx_disable_1 tx_disable_0 open drain output 2.5 v cmos transmitter disable: output used to disable a gbic module transmitter. external pull-up resistor usually resident in a gbic module is required for proper operation. b11 tx_fault_int open drain output 2.5 v cmos transmitter fault interrupt: open drain output interrupt to signal a tx_fault condition. b14 rx_los_int open drain output 2.5 v cmos receiver loss of signal interrupt: open drain output interrupt to signal an rx_los condition. g15 mod_def_int open drain output 2.5 v cmos module definition interrupt: open drain output interrupt to signal a mod_def condition. l19 i 2 c_clk output 2.5 v cmos i 2 c reference clock: clock used for i 2 c bus interface. f24 g24 e22 g20 h24 e23 f22 j24 g23 g22 i 2 c_data_9 i 2 c_data_8 i 2 c_data_7 i 2 c_data_6 i 2 c_data_5 i 2 c_data_4 i 2 c_data_3 i 2 c_data_2 i 2 c_data_1 i 2 c_data_0 input/ output 2.5 v cmos i 2 c data bus: data i/o for the i 2 c bus interface. led interface a19 led_clk output 2.5 v cmos led clock: clock output for the led block. table 1. ixf1110 si gnal pins (continued) ball designator signal name type standard signal description
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 21 document #: 250210 revision #: 004 rev. date: december 18, 2002 a20 led_data output 2.5 v cmos led data: data output for the led block. k18 led_latch output 2.5 v cmos led latch: latch enable for the led block. jtag interface aa24 tclk input 2.5 v cmos jtag test clock: reference clock for jtag. t16 tms input 2.5 v cmos jtag test mode select: selects test mode for jtag. ac18 tdi input 2.5 v cmos jtag test data input: test data sampled with respect to the rising edge of tck. n18 trst input 2.5 v cmos jtag test reset: reset input for jtag test. y24 tdo output 2.5 v cmos jtag test data output: te s t data driven with respect to the falling edge of tck. system interface aa5 clk125 input 2.5 v cmos 125 mhz reference clock: input clock to pll. c21 clk50 input 2.5 v cmos spi4-2 reference clock: input clock to spi4-2 rx pll. input range is 40 mhz to 50 mhz. this clock multiplied by eight must equal the required spi4-2 data clock frequency. y4 sys_res input 2.5 v cmos system reset: system hard reset (active low). table 1. ixf1110 signal pins (continued) ball designator signal name type standard signal description
intel ? ixf1110 10-port gigabit ethernet media access controller 22 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 table 2. ixf1110 power supply signal descriptions ball # signal name type standard signal description d1, e24, p7, p18, v6, v11, v14, v18 avdd ? ? 1.8 v analog power supply: 1.8 v supply for analog circuits. n3, n22, p3, p22, v10, v15, y1 avdd2 ? 2.5 v analog power supply: 2.5 v supply for analog circuits. d6, d10, d11, d15, d19, d20, e21, f4, f21, h10, h15, j4, j11, j14, k3, k4, k5, k8, k17, k21, l9, l11, l14, l16, p9, p11, p14, p16, r4, r8, r17, r21, t11, t14, u10, u15, w4, w21, aa6, aa10, aa15, aa19, ab4 vdd ? ? 1.8 v digital power supply: 1.8 v core supply. b4, b8, b12, b13, b17, b21, d2, d23, f8, f12, f13, f17, h2, h6, h19, h23, j12, j13, m2, m6, m9, m12, m13, m16, m19, m23, n2, n6, n9, n12, n13, n16, n19, n23, t12, t13, u2, u6, u19, u23, w8, w12, w13, w17, aa2, aa23, ac4, ac8, ac12, ac13, ac17, ac21 vdd2 ? ? 2.5 v digital power supply: 2.5 v i/o supply. b6, b10, b15, b19, c4, d4, d5, d8, d12, d13, d17, d21, d22, d24, e1, f2, f6, f10, f15, f19, f23, g10, h4, h8, h12, h13, h17, h21, j10, j15, j21, j23, k2, k6, k9, k11, k14, k16, k19, k20, k23, k24, l3, l6, l10, l12, l13, l15, l24, m3, m4, m8, m11, m14, m17, m18, m21, n4, n8, n11, n14, n17, n21, p1, p10, p12, p13, p15, p21, p23, p24, r1, r2, r3, r6, r9, r10, r11, r14, r16, r19, r23, r24, t7, t8, t9, t10, t15, t17, t18, t19, t21, t23, u4, u7, u8, u12, u13, u16, u17, u21, v2, v3, v13, v16, w2, w3, w5, w6, w7, w10, w15, w19, w20, w23, y2, y3, y8, y12, y13, y15, y16, y18, aa1, aa3, aa4, aa7, aa8, aa12, aa13, aa14, aa17, aa21, ab6, ab7, ab10, ab17, ab21, ab23, ac6, ac7, ac10, ac11, ac15, ac19, ac20, ad21 gnd ? ? ground: ground return for all signals.
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 23 document #: 250210 revision #: 004 rev. date: december 18, 2002 2.2 power sequencing correct operation requires a power-up and power-down sequence. failure to follow this sequence can result in damage to the device. the sequence described in this section covers digital and analog supplies for the device. ensure that the 1.8 v supplies (vdd/avdd) are applied an d stable prior to the application of the 2.5 v supplies (vdd2/avdd2). note: if the 2.5 v supplies (vdd2/avdd2) exceed the 1.8 v core supplies (vdd/avdd) by more than 2.0 v during power-up or power-down, damage can occur to the esd structures within the analog ios. since the power-down sequence is the reverse of the power-up sequence, remove the 2.5 v supplies (vdd2/avdd2) prior to the remova l of the 1.8 v core supplies (vdd/vdd2). table 3. ixf1110 unused balls/reserved ball # signal name type standard signal description a5, a6, c10, c15, g7, g8, h22, j22, k7, l21, l23, m1, m7, n1, n5, n7, n20, p4, p5, p6, p17, p19, p20, r5, r13, r18, r20, r22, t1, t6, u1, v1, v8, v9, v19, w1, w16, w18, y7, y10, y11, y14, aa11, aa20, aa22, ab3, ab5, ab8, ab18, ab19, ab20, ab22, ad4, ad5, ad6, ad7, ad8, ad17, ad19, ad20 n/c ? ? no connection. a2, a3, a22, a23, a24, b1, b2, b23, b24, c1, c24, ab1, ab24, ac1, ac2, ac23, ac24, ad1, ad2, ad3, ad22, ad23, ad24 no ball ? ? balls removed from substrate. a1 no pad ? ? pad removed from substrate. figure 5. power sequencing diagram time t=0 apply vdd, avdd 1.8 v supplies stable apply vdd2, avdd2 2.5 v supplies stable apply sys_res
intel ? ixf1110 10-port gigabit ethernet media access controller 24 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 table 4. power sequencing power supply power-up order time delta to next supply 1 description vdd, avdd first 0 1.8 v supplies vdd2, avdd2 second 10 s 2.5 v supplies 1. the value of 10 s given is a nominal value onl y. the exact time difference between the application of the 2.5 v analog supply will be determined by a number of factors dependent on the power management method used. the key requirement that must be met to avoid damage to the device is that the avdd2 supply must not exceed the vdd supply by more than 2 v at any time during the power-up or power-down sequence.
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 25 document #: 250210 revision #: 004 rev. date: december 18, 2002 3.0 functional descriptions 3.1 media access controller 3.1.1 general description the intel ? ixf1110 main functional block consists of a 1000 mbps ethernet media access controller (mac), supporting the following features: ? 1000 mbps full-duplex operation ? independent enable/disable of any port ? detection of length error or overly large packets ? rmon statistics and error counters ? cyclic redundancy check (crc) cal culation and er ror detection ? programmable option to: ? filter packets with errors ? filter, broadcast, multicast, and unicast address packets ? automatically pad transmitted pack ets less than the minimum frame size ? compliance with ieee 802.3x standard for flow control (symmetric pause capability) the mac is fully integrated, desi gned for use with ethernet 802.3 frame types, and is compliant with all of the required i eee 802.3 mac requirements. the mac adds preamble and start- of-frame delimiter (sfd) to al l frames sent to it (transmit path) and removes preamble and sfd on all frames received by it (receive path). a crc check is also applied to all transmit and receive packets. packets with a bad crc are marked, counted in the statistics block, and may be optionally droppe d or sent to th e spi4-2 interface. 3.1.2 mac functions section 3.1.2.1, ?padding of unders ized frames on transmit? on page 25 through section 3.1.2.4, ?pause command frames? on page 28 cover the mac functions. 3.1.2.1 padding of undersized frames on transmit the padding feature allows ethern et frames smaller than 64 byte s to be transferred across the spi4-2 interface and automatically padded up to 64 bytes by the mac. this feat ure is enabled by setting bit 7 of the diverse config regi ster = 1 (address port_index + 0x18h). see table 59 on page 106 .
intel ? ixf1110 10-port gigabit ethernet media access controller 26 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 3.1.2.2 automatic crc generation the automatic crc generation is used in conjunct ion with the padding feature to generate and append a correct crc to any incoming frame from the spi4-2 interface. this feature is enabled by setting bit 6 of the diverse config register = 1 (address port_index + 0x18h) (see table 59 on page 106 ). note: when padding of undersized fram es on transmit is enabled, the automatic crc generation must be enabled for proper operation of the ixf1110. 3.1.2.3 filtering of receive packets this feature allows the mac to filter receive packets under va rious conditions and drop the packets via an interaction with the receive fifo control. note: jumbo frames (1519 - 9600 bytes) matching the filter conditions, which would cause the frame to be dropped by the rx fifo, are not dropped. inst ead, jumbo frames that are expected to be dropped by the rx fifo, based on the filter settings in table 60, ?rx packet filter control register (addr: port_index + 0x19)? on page 107 , are sent across the spi4- 2 interface as an eop abort frame. jumbo frames matching the filter cond itions are not counted in the rx fifo number of frames removed register because they are not removed by the rx fifo. only standard packet sizes (64 - 1518 bytes) meeting the filter conditions set in the ?rx packet filter control register (addr: port_index + 0x19)? are actually dropped by the rx fifo and counted in the rx fifo number of frames removed. 3.1.2.3.1 filter on unicast packet match this feature is enabled when bit 0 of the rx packet filter control register = 1. any frame received in this mode co ntaining a unicast des tination address which doe s not match the station address is marked by the mac to be dropped. the frame is dropped if the appropriate bit in the rx fifo errored frame drop enable register = 1. otherwise, all unicast frames are sent to the spi4-2 interface. 3.1.2.3.2 filter on multicast packet match this feature is enabled when bit 1 of the rx packet filter control register = 1. any frame received in this mode co ntaining a multicast destination addr ess which does not match the port multicast address is marked by the mac to be drop ped. the frame is dropp ed if the appropriate bit in the rx fifo errored frame drop enable re gister = 1. otherwise, all multicast frames are sent to the sp i4-2 interface. 3.1.2.3.3 filter broadcast packets this feature is enabled when bit 2 of the rx packet filter control register = 1. any broadcast frame received in this mode is marked by the mac to be dropped. the frame is dropped if the appropriate bit in the rx fifo er rored frame drop enable register = 1. otherwise, all broadcast frames are sent to the spi4-2 interface.
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 27 document #: 250210 revision #: 004 rev. date: december 18, 2002 3.1.2.3.4 filter vlan packets this feature is enabled when bit 3 of the rx p acket filter control regi ster = 1. vlan frames received in this mode are marked by the mac to be dropped. the frame is dropped if the appropriate bit in the rx fifo errored frame drop enable register = 1. otherwise, all vlan frames are sent to the spi4-2 interface. 3.1.2.3.5 filter pause packets this feature is enabled when bit 4 of the rx p acket filter control regi ster = 0. pause frames received in this mode are marked by the mac to be dropped. the frame is dropped if the appropriate bit in the rx fifo errored frame dr op enable register = 1. otherwise, all pause frames are sent to the spi4-2 interface. 3.1.2.3.6 filter crc errored packets this feature is enabled wh en bit 5 of the rx pack et filter control regist er = 0. frames received with an errored crc are marked as bad frames and may optionally be dr opped in the rx fifo. otherwise, the frames are sent to the spi4-2 inte rface and may be dropped by the switch or system controller (see table 6 ). table 5. pause packets drop enable behavior pause frame pass frame drop en actions 10 packets are passed to the spi4-2 interface. they are not marked as bad and are sent to the switch or network processor. 00 packets are marked as bad but not dropped in the rx fifo. these packets are sent to the spi4-2 interface, but with an eop abort code to the switch or network processor. 11 packets are not marked as bad and sent to the switch or network processor, regardless of the frame drop en setting. 01 pause packets are marked as bad, are dropped in the rx fifo, and never appear at the spi4-2 interface. table 6. crc errored packets drop enable behavior crc errored pass frame drop en actions 10 packets are passed to the spi4-2 interface. they are not marked as bad and are sent to the switch or network processor. 00 packets are marked as bad but not dropped in the rx fifo. these packets are sent to the spi4-2 interface, but with an eop abort code to the switch or network processor. 11 packets are not marked as bad and are sent to the switch or network processor regardless of the frame drop en setting. 01 crc errored packets are marked as bad, dropped in the rx fifo, and never appear at the spi4-2 interface.
intel ? ixf1110 10-port gigabit ethernet media access controller 28 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 3.1.2.4 pause command frames the mac acts on any pause command frames recei ved from the link partner by checking the entire frame and verifying that it is a valid pa use control frame addresse d to either the multicast address (01-80-c2-00-00-01 as specified in ieee 8 02.3, annex 31b) or the station address. if the pause frame is valid, the transm it side of the mac pauses for the required number of pause quanta, as specified in ie ee 802.3u, clause 31 (see table 5 ). note: pause does not begin until completion of the frame currently being transmitted. 3.1.3 fiber operation the data path in the mac is an internal 10-bit interface, as described in the ieee 802.3z standard. it is connected directly to an internal serdes block for se rialization/dese rialization and transmission/reception on the fibe r medium to/from the link partner. the mac contains all the pcs (8b/10b encoding and 10b/8b decoding) required to encode and decode the data. the mac also supports auto-n egotiation per the ieee 802.3z standard via access to the tx config word, rx config word, and diverse config registers (see table 57 on page 105 , table 58 on page 106 , and table 59 on page 106 ). by default, ixf1110 auto-negotiation is disabled by register bit 5 (an_enable) of the ?diverse config register (addr: port_index + 0x18)? . when auto-negotiation is disabled, the ixf1110 can operate in forced mode, which is 1000 mbps full duplex only. this is equivalent to entering the state an_disable_link_ok as described in fi gure 37-6 of ieee 802.3. the ixf1110 can pass packets when auto-negotiation is disabled only when the internal synchronization state machine indicates that the sync_status is ok as described in figure 36-9 of ieee 802.3. note: packet ipg must contain a minimum of three cons ecutive /i1/ or /i2/ ordered sets per ieee 802.3 for correct operation. note: in forced mode, the tx spi4-2 status bus (tstat[1:0]) is held in the satisfied state until sync_status is ok. this prevents the tx fifo fr om being filled prior to transmission of packets. 3.1.4 auto-negotiation in the ixf1110, auto-negotiation is carried out by an internal state machine within the mac. the ixf1110 is fully ieee 802.3z standard compliant. there are three registers involved in this auto-negotiation process: rx config word, tx config word, and diverse config: ? the rx config word register performs the operation of the auto-negotiation link partner ability register (see table 57, ?rx config word register (addr: port_index + 0x16)? on page 105 ) ? the tx config word register performs the operation of the auto-negotiation advertisement register (see table 58, ?tx config word register (addr: port_index + 0x17)? on page 106 ? the diverse config register enables auto-negotiation (see table 59, ?diverse config register (addr: port_index + 0x18)? on page 106 )
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 29 document #: 250210 revision #: 004 rev. date: december 18, 2002 the tx config word register must be writte n to program the modes advertised. the diverse config register bit 5 (an_enable) must be written to enable auto-negotiation. the rx config word register must be polled to determine when auto-negotiation is complete and to determine the link mode. the following mac registers must be programmed to match the results upon completion: ? link: table 66, ?link led enable register (addr: 0x502)? on page 119 (addr: 502) ? flow control: if the link partner does not suppor t flow control, the fc enable register (addr: port index + 0x12) must be updated to reflect this change (see table 54, ?fc enable register (addr: port_index + 0x12)? on page 104 to restart auto-negotiation, bit 5 of the diverse config register (an_enable) must be de-asserted, then re-asserted. 3.1.5 forced mode operation the fiber operation of the mac can be forced to operated at 1000 mbps, full duplex without completion of the auto negotiation function. in this mode, the receive path of the mac must achieve synchronization with the lin k partner. once this has been achieved, the transmit path of the mac will be enabled to allow data transmission, which is known as ?forced mode? operation. forced mode is limited to operation with a link pa rtner that operates with a full-duplex link at a speed of 1000 mbps. forced mode is enabled by regi ster bit 5 (an_enable) in the ?diverse config register (addr: port_index + 0x18)? . by default, the ixf1110 is set to forced mode operation. 3.1.6 jumbo packet support the ixf1110 supports the concept of jumbo frames . the jumbo frame length is dependent on the application, and the ixf1110 design has been optimized for 9.6 k jumbo frame length. lengths larger than this can be programmed, but will limit system performance. the value programmed into the max frame size regi ster (addr: port_index + 0x0f) determines the maximum length frame size the mac can rece ive or transmit without activating any error counters, and without truncation. the max frame size register (addr : port_index + 0x0f) bits 13:0 set the frame length. the default value programmed into this register is 0 x05ee (1518). the value is internally adjusted by +4 if the frame has a vlan tag. the overall programmable maximum is 0x3fff or 16383 bytes. the register should be programmed to 0x2667 for the 9.6 k length jumbo frame for which the ixf1110 is optimized. the rmon counters are also affected for jumbo frame support as follows: rx statistics: ? rxoctetstotalok (addr: port_index + 0x20) ? rxpkts1519tomaxoctets (addr: port_index + 0x2b) ? rxfcserrors (addr: port_index + 0x2c) ? rxdataerror (addr: port_index + 0x02e) ? rxalignerrors (addr: port_index + 0x2f)
intel ? ixf1110 10-port gigabit ethernet media access controller 30 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 ? rxlongerrors (addr: port_index + 0x30) ? rxjabbererrors (addr: port_index + 0x31) ? rxverylongerrors (addr: port_index + 0x34) tx statistics: ? txoctetstotalok (addr: port_index + 0x40) ? txpkts1519tomaxoctets (addr: port_index + 0x4b) ? txexcessivelengthdrop (addr: port_index + 0x53) ? txcrcerror (addr: port_index + 0x56) the ixf1110 device checks the crc for all legal length jumbo frames (frames between 1519 and the max frame size). on transmission, the ma c can be programmed to append the crc to the frame or check the crc and increm ent the appropriate counter. on reception, the mac transmits these frames across the spi4-2 in terface (jumbo frames with a ba d crc cannot be dropped and are sent across the spi4-2 interface). if the receive frame has a bad crc, the appropriate counter is incremented and the eop abort code is set in the spi4-2 control word. jumbo frames also impact flow control. the maximum frame size needs to be taken into account when determining the fifo wate rmarks. the current transmission must be completed before a pause frame can be transmitted (needed when the receiver fifo high watermark has been exceeded). if the current transmis sion is a jumbo frame, the delay may be significant and increase data loss due to insufficient available fifo space. 3.1.7 rmon statistics support 3.1.7.1 rmon statistics the ixf1110 supplies rmon statistics via the cpu in terface. these statistics are available in the form of counter values that can be accessed at specific addresses in the ixf1110 memory map. once read, these counters automati cally reset and begin counting from zero. a separate set of rmon statistics is available for each mac device in the ixf1110. implementation of the rmon statistics block is similar to the functionality provided by existing intel switch and router products. this implementation allows the ixf1110 to provide all of the rmon statistics group as defined by rfc2819. the ixf1110 supports the rmon rfc2819 group 1 statistics counters. table 7 notes the differences and additional statistics registers suppo rted by the ixf1110 that are outside the scope of the rmon rfc2819 document.
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 31 document #: 250210 revision #: 004 rev. date: december 18, 2002 table 7. rmon additional statistics registers rmon ethernet statistics group 1 statistics type ixf1110 equivalent statistics type definition of rmon versus ixf1110 documentation etherstatsindex integer32 n/a n/a n/a etherstatsdatasource object identifier n/a n/a n/a etherstatsdropevents counter32 rx/tx fifo number of frames removed counter 32 see table note 1. etherstatsoctets counter32 rxoctetstotalok rxoctetsbad txoctetstotalok txoctetsbad counter 32 note: the ixf1110 has two counters for rx and tx that use different naming conventions for total octets and octets bad. these counters need to be combined to meet the rmon spec. etherstatspkts counter32 rx/txucpkts rx/txbcpkts rx/txmcpkts counter 32 note: the ixf1110 has three counters for etherstatspkts that need to be combined to give the total packets as defined by the rmon spec. etherstatsbroadcastpkts counter32 rx/txbcpkts counter 32 ok etherstatsmulticastpkts counter32 rx/txmcpkts counter 32 see table note 2. etherstatscrcalignerrors counter32 rxalignerrors rxfcserrors txcrcerror counter 32 note: the ixf1110 has two counters for alignment and crc errors for the rx side only. the ixf1110 has crcerror for the tx side. 1. the rmon spec requires that this is, "the tota l number of events where packets were dropped by the probe due to a lack of resources. note that this number is not necessarily the number of packets dropped; it is the number of times this condition has been det ected." the rx/tx fifo number of frames removed register in the ixf1110 supports this and will increment when either an rx or txfifo has over flowed. if any ixf1110 programmable packet fi ltering is enabled, the rx/tx number of frames removed register increments with every frame removed in addition to the existing frames counted due to fifo overflow. 2. the ixf1110 has an extra counter rx/txucpkts that can be used. 3. the ixf1110 has an extra counter rx/txpktstomaxoctets that can be used in addition to the rmon stats. this is required to accommodate the jumbo packet frames requirement.
intel ? ixf1110 10-port gigabit ethernet media access controller 32 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 3.1.7.2 conventions the following conventions are used throughout the rmon mib and its companion documents. ? good packets : error-free packets that have a valid fra me length. for example, on ethernet, good packets are error-free packets that are between 64 octets long and 1518 octets long. they follow the form defined in ieee 802.3, section 3.2. ? bad packets : packets that have proper framing and are therefore recognized as packets, but contain errors within the packet or have an invalid length. for example, on ethernet, bad packets have a valid preamble and sfd, but ha ve a bad crc, or are either shorter than 64 octets or longer than 1518 octets. 3.1.7.3 additional statistics the following lists additional ixf1110 registers that support features not documented in rmon. etherstatsoversizepkts counter32 rxlongerrors txexcessivelengthdrop counter 32 ok etherstatsjabbers counter32 rxjabbererrors counter 32 ok etherstatscollisions counter32 txsinglecollisions txmultiplecollisions txlatecollisions txtotalcollisions counter 32 ok note: registers exist on the tx side but should not increment since the ixf1110 only supports full- duplex. etherstatspkts64octets counter32 rx/txpkts64octets counter 32 ok etherstatspkts65to127octets counter32 rx/txpkts65to127octets counter 32 ok etherstatspkts128to255octets counter32 rx/txpkts128to255octets counter 32 ok etherstatspkts256to511octets counter32 rx/txpkts256to511octets counter 32 ok etherstatspkts512to1023octets counter32 rx/txpkts512to1023octets counter 32 ok etherstatspkts1024to1518octet s counter32 rx/txpkts1024to1518octets counter 32 see table note 3. etherstatsowner ownerstring n/a n/a n/a etherstatsstatus entrystatus n/a n/a n/a table 7. rmon additional statistics registers (continued) 1. the rmon spec requires that this is, "the total number of events where packets were dropped by the probe due to a lack of resources. note that this number is not necessarily the number of packets dropped; it is the number of times this condition has been detec ted." the rx/tx fifo number of frames removed register in the ixf1110 supports this and will increm ent when either an rx or txfifo has over flowed. if any ixf1110 programmable packet fi ltering is enabled, the rx/tx number of frames removed register increments with every frame removed in addition to the existing frames counted due to fifo overflow. 2. the ixf1110 has an extra counter rx/txucpkts that can be used. 3. the ixf1110 has an extra counter rx/txpktstomaxoctet s that can be used in addition to the rmon stats. this is required to accommodate the jumbo packet frames requirement.
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 33 document #: 250210 revision #: 004 rev. date: december 18, 2002 ? mac (flow) control frames ? vlan tagged frames ? sequence errors ? symbol errors ? crc errors these additional counters allow for additional differentiation over and above standard rmon probes. note: a packet transfer with an invalid 10-bit symbol will not always update th e statistics registers correctly. ? behavior: the ixf1110 8b10b decoder substitutes a va lid code word octet in its place. the packet transfer is aborted and ma rked as bad. the new internal le ngth of the packet is equal to the byte position where the invalid symbol was. no packet fragments are seen at the next packet transfer. ? issue: if the invalid 10-bit code is inserted in a byte position of 64 or greater, expected rx statistics are reported. however, if the invalid c ode is inserted in a byte position of less than 64, expected rx statistics are not stored. 3.1.8 transmit pause control interface the transmit pause control interface is completely asynchronous. it cons ists of four address signals (txpauseadd[3:0]) and a strobe signal (txp ausefr). the required ad dress for this interface operation is placed on the txpauseadd[3:0] pins and the txpausefr is pu lsed high and then returned low. refer to figure 32, ?transmit pause control interface diagram? on page 83 and table 27, ?transmit pause contro l interface parameters? on page 83 . the valid decodes for the txpauseadd[3:0] signals are shown in table 8 . figure 6 illustrates the transmit pause control interface. table 8. valid decodes for txpauseadd[3:0] txpauseadd[3:0] operation of tx pause interface 00h sends out a pause frame on every port wi th a pause_time = zero (cancels all previous pause commands). 01h to 0ah sends a pause frame out on the selected port with pause_time = to the value programmed into that port?s register set 0bh to 0eh reserved. these are invalid decodes and shoul d not be used. the tx pause interface will not operate under these conditions. 0fh sends a pause frame out on every port with pause_time = to the value programmed into that ports register set.
intel ? ixf1110 10-port gigabit ethernet media access controller 34 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 figure 6. transmit pause control interface txpausefr strobe 1: y port 0 : transmit pause packet txpauseadd(0) txpauseadd(1) txpauseadd(3) txpauseadd(2) this example shows the following conditions: strobe 2: y all ports : transmit pause packet with pause_time = 0 strobe 3: y port 7 : transmit pause packet
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 35 document #: 250210 revision #: 004 rev. date: december 18, 2002 3.2 system packet interf ace level 4 phase 2 the system packet interface level 4 phase 2 ( spi4-2) provides a high-sp eed connection to a network processor or an asic. the interface implem ented on the ixf1110 operates at data rates up to 12.8 gbps and supports up to ten 1 gbps mac channels. the data path is 16 lanes wide in each direction, with each lane opera ting from 640 mbps up to 800 mbps. port a ddressing, start/end packet control, and erro r control codes are all transferred ?in-band? on the data bus. in-band addressing supports up to 10 ports . separate transmit and receive fi fo status lines are used for flow control. by keeping the fifo status info rmation out-of-band, th e transmit and receive interfaces may be de-coupled to operate independently. figure 7 provides an overview of the ixf1110 spi4-2 interface. 3.2.1 data path transfer of complete packets or shorter bursts is controlled by the programmed maxburst1 or maxburst2 in conjunction with the fifo status bus. the maximum configured payload data transfer size must be a multiple of 16 bytes. control words are inserted between burst transfers only. once a transfer begins, data words are sent uninterrupted until an end-of-packet, or until a multiple of 16 bytes is reached as programmed in maxb urst1 and maxburst2. the interval between the end of a given transfer and the next payload control word (marking the start of another transfer) consists of zero or more idle control words and/or training patterns. note: the system designer should be aw are that the mac transfer thres hold register must be set to a value which exceeds maxburst1 number of bytes. otherwise, a tx fifo under-run may result. the minimum and maximum supported packet length s are determined by the application. because the ixf1110 is targeted at the ethernet environment, the minimum frame size is 64 bytes and the maximum frame size is 1522 bytes for vlan packets (1518 bytes for non-vlan packets). for larger frames, adjust the max fram e size register value, seen in table 53 on page 104 . for ease of implementation, successive start-of-packets must o ccur not less than eight cycles apart, where a cycle is one control or data word. the gap between shorter packets is filled with idle control words. figure 7. ixf1110 spi4-2 interfacing with the network processor or forwarding engine mac network processor or forwarding engine tsclk tsclk tdat[15:0]+/- spi-4.2 signals tstat[1:0] tstat[1:0] tdat[15:0]+/- tdclk+/- tdclk+/- tctl+/- tctl+/- rsclk rsclk rstat[1:0] rstat[1:0] rdclk+/- rdclk+/- rdat[15:0]+/- rdat[15:0]+/- rctl+/- rctl+/-
intel ? ixf1110 10-port gigabit ethernet media access controller 36 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 note: data packets with frame lengths less than 64 bytes should not be transferred to the ixf1110 unless packet padding is enabled. if this rule is disr egarded, unwanted fragments may be generated on the network at the serdes interface. figure 8 on page 36 shows cycle-by-cycle behavior of the data path for valid state transitions. the states correspond to the type of words transferred on the data path. transitions from the ?data burst? state (to ?payload control? or ?idle control?) are possible on ly on the integer multiples of eight cycles (corresponding to multiples of 16- byte segmentations) or upon end-of-packet. a data burst must immediately follow a payload control word on the next cycl e. arcs not annotated correspond to single cycles. in the ixf1110, the rx fifo status channel opera tes in a ?pessimistic mode.? it is termed as pessimistic because it has the longest latency and largest impact on usable bandwidth. however, as a dip-2 check error is a rare event, there will be no ?real world? effect on bandwidth utilization and no possibility of data loss. for example, if th ere is a dip-2 check error found, all previously granted credits are cancelled and the internal stat us for each channel is set to satisfied. any current data burst in transmission is completed. no new credits are granted until a complete fifo status cycle has been received and validated by a correct dip-2 check. this is the only method of operation that can eliminate the possibility of an overrun in the link partner device. 3.2.1.1 control words a common control word format is used in both the transmit and receive interfaces. table 9 describes the fields in the control word. when inserted in the data path, the control word is aligned such that its msb is sent on the msb of the transm it or receive data lines. a payload control word that separates two adjacent burst tr ansfers contains status information pertaini ng to the previous transfer and the following transfer. table 10 provides a list of control-word definitions. figure 8. data path state diagram
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 37 document #: 250210 revision #: 004 rev. date: december 18, 2002 table 9. control word format bit position label description 15 type control word type. set to either of the following values: 1: payload control word (payload transfer will immediately foll ow the control word). 0: idle or training control word. 14:13 eops end-of-packet (eop) status. set to the following values according to the status of the immediately preceding payload transfer. 0 0: not an eop. 0 1: eop abort (application- specific error condition). 1 0: eop normal termination, 2 bytes valid. 1 1: eop normal termination, 1 byte valid. eops is valid in the first control word follow ing a burst transfer. it is ignored and set to ?0 0? otherwise. 12 sop start-of-packet. set to 1 if the payload transfer immediately following the control word corresponds to the start of a packet. set to 0 otherwise. set to 0 in all idle and training control words. 11:4 adr port address. 8-bit port address of the payload data transfe r immediately following the control word. none of the addresses are reserved (all are available for payload transfer). set to all zeroes in all idle control words. set to all ones in all training control words. 3:0 dip-4 4-bit diagonal interleaved parity. 4-bit odd parity computed over the current control word and the immediately preceding data words (if any) following the last control word. table 10. control word definitions bit [15:12] next word status prior word status meaning 0 0000 idle continued idle, not eop, training control word 1 0001 reserved reserved reserved 2 0010 idle eop w/abort idle, abort last packet 3 0011 reserved reserved reserved 4 0100 idle eop w/ 2 bytes idle, eop with 2 bytes valid 5 0101 reserved reserved reserved 6 0110 idle eop w/ 1 byte idle, eop with 1byte valid 7 0111 reserved reserved reserved 8 1000 valid none valid, no sop, no eop 9 1001 valid/sop none valid, sop, no eop a 1010 valid eop w/abort valid, no sop, abort b 1011 valid/sop eop w/abort valid, sop, abort c 1100 valid eop w/ 2 bytes valid, no sop, eop with 2 bytes valid
intel ? ixf1110 10-port gigabit ethernet media access controller 38 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 the spi4-2 specification details all available payload control words and should be used to reference the specific meaning of each. the ixf 1110 supports all require d functions per this specification. however, there are various specifics in the way certain control words affect the balance of the ixf1110 operation, such as how the device deals with eop aborts. the spi4-2 specification allows th e eop abort payload control word, which signals that the data associated with a particular fr ame is errored and should be dropp ed, or errored and dropped by the far-end link partner. in the ixf1110, all tx spi4-2 transfers that end with an eop abort code have the tx serdes crc corrupted. this is tr ue regardless of th e mac configuration. figure 9 shows per-port state transitions at control-wo rd boundaries. at any given time, a port may be active (sending data), paused (not sending da ta but pending the completion of an outstanding packet), or inactive (not sending data, no outstanding packet). 3.2.1.2 dip4 figure 10 shows the range over which the diagonal in terleaved parity (dip-4) parity bits are computed. a functional description of calculating th e dip-4 code is given as follows. assume that the stream of 16-bit data word s are arranged as shown in figure 11 , msb at the left most column, time moving downward. (the first wo rd received is at the top of the figure; the last word is at the bottom of the figure.) the parity bits are generated by summing diagonally (in the control word, the space occupied by the dip-4 code (bits a, b, c, d) is set to all 1s during encoding). the first 16- bit result is split into two bytes, which are adde d to each other modulo-2 to produce an 8-bit result. d 1101 valid eop w/ 2 bytes valid, sop, eop with 2 bytes valid e 1110 valid eop w/ 1 byte valid, no sop, eop with 1byte valid f 1111 valid eop w/ 1 byte valid, sop, eop with 1byte valid table 10. control word definitions (continued) bit [15:12] next word status prior word status meaning figure 9. per-port state diagram with transitions at control words port [ n ] inactive port [ n ] active port [ n ] paused pc[ n ] & -sop (ic i pc[- n ]) & -eop pc[ n ] & eop & sop pc[ n ] & sop (ic i pc[- n ]) & eop pc[ n ] & -eop & -sop key: ic: idle control word pc[ n ]: payload control word for port n pc[- n ): payload control word for a port other than port n sop: start-of-packet in payload control word -sop: no start-of-packet in payload control word eop: end-of-:acket in control word -eop: no end-of-packet in control word &: and i: or
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 39 document #: 250210 revision #: 004 rev. date: december 18, 2002 the 8-bit result is then divided into two 4-bit ni bbles, which are added to each other modulo-2 to produce the final dip-4 code. the procedure describe d applies to either parity generation on the rx path or to check parity on the tx path. figure 10. dip-4 calculation boundaries a9039-01 payload payload dip-4 codewords control control control control
intel ? ixf1110 10-port gigabit ethernet media access controller 40 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 3.2.2 start-up parameters 3.2.2.1 calendar_len calendar_len specifies the length of each cal endar sequence. as the ixf1110 is a 10-port device, calendar_len is fixed at 10 for both tx and rx data paths. figure 11. dip-4 calculation algorithm a9040-01 1st spi-4 phase ii data word of incoming burst 10 101 01 100 01 011 1 10 10101 0 11 10101 0 01 00000 0 16-bit parity sum (dip16[15:0]) 01 00 00 00 01 00 dip4 parity bits (dip4[3:0]) 8-bit parity sum dip4[3] = dip16[15] dip16[11] dip16[7] dip16[3] dip4[2] = dip16[14] dip16[10] dip16[6] dip16[2] dip4[1] = dip16[13] dip16[9] dip16[5] dip16[1] dip4[0] = dip16[12] dip16[8] dip16[4] dip16[0] a, b, c and d are all set to 1 during encoding. 0 321 control word: not included in parity calculations below 2nd spi-4 phase ii data word of incoming burst 3rd spi-4 phase ii data word of incoming burst 4th spi-4 phase ii data word of incoming burst 5th spi-4 phase ii data word of incoming burst 6th spi-4 phase ii data word of incoming burst 7th spi-4 phase ii data word of incoming burst 8th spi-4 phase ii data word of incoming burst 10 110 10 111 00 010 0 00 001 10 100 10 011 0 00 110 00 001 00 000 0 11 010 11 111 10 000 0 00 000 00 001 00 010 0 00 010 10 111 00 000 0 11 010 10 100 01 011 0 10 110 00 000 00 000 0 11 110 0a 0bc 00 010 d 0 321 4 765 8 11 10 9 12 15 14 13 to 2 to 3 to 4 to 5 to 6 to 7 to 8 to 9 2 3 4 5 6 7 8 9 00 100 1w 1xy 00 010 z each bit of this 16-bit parity sum is the result of a xor operation along the corresponding dashed line. control word: included in parity calculations (contains the results of parity for the 8 spi-4 phase ii data words above and this control word)
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 41 document #: 250210 revision #: 004 rev. date: december 18, 2002 3.2.2.2 calendar_m calendar_m specifies the number of times th e calendar port status sequence is repeated between the framing and dip2 cycle of the calendar sequence. in the ixf1110, the tx path calendar_m is fixed at 1; thus, the port status for ports 0 - 9 will be transmitted only once betw een the framing and dip2 cycle of the calendar sequence. in the ixf1110, the rx path calendar_m is configurable. the default value of expected rx calendar_m is 1 as per the tx path. in table 85, ?spi4-2 rx calendar register (addr: 0x702)? on page 141 , bits 3 to 0 specify cal_m, which is the number of times the calendar sequence will be repeated ov er the default value of 1. the default value for cal_m is 0, thus the default value of both tx and rx calendar_m parameters is 1. 3.2.2.3 dip2_thr dip2_thr is a parameter specifying the number of consecutive correct dip2 s required by the rx spi4-2 to validate a calendar sequence and ther efore terminate sending training sequences. in table 85, ?spi4-2 rx calendar register (addr: 0x702)? on page 141 , bits 19 to 16 specify this parameter. the default value for dip2_thr is 1. 3.2.2.4 loss_of_sync loss_of_sync is a parameter specifying the nu mber of consecutive fr aming calendar cycles required to indicate a loss of synchronization and ther efore restart training sequences. table 85, ?spi4-2 rx calendar register (addr: 0x702)? on page 141 , bits 11 to 8 specify this parameter. the default value for loss_of_sync is three. 3.2.2.5 data_max_t data_max_t is an rx spi4-2 parameter specify ing the interval between transmission of periodic training sequences. in table 84, ?spi4-2 rx training register (addr: 0x701)? on page 140 , bits 15 to 0 specify this parameter. th e default value for data_max_t is 0x0000, which disables periodic training sequence transmission. 3.2.2.6 rep_t rep_t is an rx spi4-2 parameter specifying the num ber of repetitions of the training sequence to be scheduled every data_max_t interval. in table 84, ?spi4-2 rx training register (addr: 0x701)? on page 140 , bits 23 to 16 specify this parameter. the default value for rep_t is 0x00. 3.2.2.7 dip4_unlock dip4_unlock is a tx spi4-2 parameter specifyi ng the number of consecutive incorrect dip4 fields to be detected in order to declare loss of synchronization and drive tstat[1:0] bus with framing. in table 86, ?spi4-2 tx synchronization register (addr: 0x703)? on page 142 , bits 15 to 8 specify this parameter. the default value for dip4_unlock is 0x4.
intel ? ixf1110 10-port gigabit ethernet media access controller 42 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 3.2.2.8 dip4_lock dip4_lock is a tx spi4-2 parameter specifying th e number of consecutive co rrect dip4 fields to be detected in order to declar e synchronization achieved and en able the calendar sequence. in table 86, ?spi4-2 tx synchronization register (addr: 0x703)? on page 142 , bits 7 to 0 specify this parameter. the default value for dip4_lock is 0x20. 3.2.2.9 maxburst1 maxburst1 is an rx spi4-2 parameter specifying the maximum number of 16 byte blocks that may be transmitted when the asso ciated fifo status indicates ?s tarving?. bits 24 to 16 of the spi4-2 rx burst size register specify this parameter. the default value for maxburst1 is 0x006, indicating a maxburst1 of 96 bytes [see section 83, ?spi4-2 rx bu rst size register (addr: 0x700)? on page 140 ]. 3.2.2.10 maxburst2 maxburst2 is an rx spi4-2 parameter specifying the maximum number of 16 byte blocks that may be transmitted when the associ ated fifo status indicates ?hungry?. bits 8 to 0 of the spi4-2 rx burst size register sp ecify this parameter. the default value for maxburst2 is 0x002, indicat- ing a maxburst2 of 32 bytes (see section 83, ?spi4-2 rx burst size register (addr: 0x700)? on page 140 ). 3.2.3 training sequence for dyna mic phase alignment (data path de-skew) 3.2.3.1 training at start-up the spi4-2 specification states that on power-up or after a reset, the training sequence (as defined in the spi4-2 specification) is se nt indefinitely by the source side until it receives valid fifo status on the fifo bus. the specificatio n also states that it is possible for the bus de-skew to be completed after one training sequence takes place. it is unlikely that the bu s can be de-skewed in a single training sequence because of the presence of both random and determ inistic jitter. the only way to account for the random element is to de termine an average over repeated training sequences. since the required number of repeats is dependent on several characteristics of the system in which the ixf1110 is being used, power on training (or training following loss of synchronization) will continue until synchroniza tion is achieved and the calendar is provisioned. the length of power on training will not be a fixed number of repeats. the number of training sequence rep eats could be fairly large (16, 32, or 64). if this is necessary every time training is required, a significant use of interface bandwidth is needed just to train and de-skew the data path. this is only done at power- up or reset for an optimal starting point interface. after this, periodic training provides a better adjustment and a substantially lower bandwidth overhead. 3.2.3.2 periodic training a scheduled training sequence is sent at leas t once every pre-config ured bounded interval (data_max_t) on bot h the transmit and receive paths. these training se quences are used by the receiving end of each interface for de-skewing bit arrival times on the data and control lines. the sequence allows the receiving end to correct for relative skew differ ence of up to +/- 1 bit time. the
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 43 document #: 250210 revision #: 004 rev. date: december 18, 2002 training sequence consists of one (1) idle control word followed by one or more repetitions of a 20- word training pattern consisting of 10 (repeated) training-control words fo llowed by 10 (repeated) training-data words. the initial idle control word removes dependencies of the dip-4 in the training control words from preceding data words. assuming a maximum of +/- bit ti me alignment jitter on each line, and a maximum of +/- bit time relative skew between lin es, there are at least eight bit times when a receiver can detect a training contro l word prior to de-skew. the traini ng data word is chosen to be orthogonal to the training control word. in the ab sence of bit errors in the training pattern, a receiver should be able successfully to de-skew the data and control lines with one training pattern. the sending side of the data path on both the transmit and receive inte rfaces must schedule the training sequence at least on ce every data_max_t cycles. note: data_max_t may be set to zero, disabling periodic training on the interface (refer to table 84, ?spi4-2 rx training register (addr: 0x701)? on page 140 ). this is done when a system shows very little drift during normal operation, and no fi ne-grain correction on an on-going basis is needed. this allows the maximum possible bandwidth for data tran sfer. the transmit and receive interface training sequences ar e scheduled independently. 3.2.3.3 training in a practical implementation the oif standard states that it should be possibl e to train and de-skew the data input in a single training cycle. howe ver, from the research carried out and th e variances in jitter and skew due to board layout and clock tolerance issues, some sort of averaging over seve ral repeated training patterns is required to reliably determine the optimal point at which to capture the incoming data. this is true for both static alignment and dyna mic phase alignment. ther efore, several training patterns are required for an average. the more training patterns, the more accurate the average. the de-skew circuit in the ixf1110 uses dyna mic phase alignment with a typical averaging requirement of 32 training patterns required to deliver a reliable result. during power-on training, an unlimited number of training cycles is sent by th e data sourcing device. (the standard states that training must be sourced until a calendar has been provisioned.) in the ixf1110, the de-skew circuit waits until completion of its programmed aver age over the training pa tterns, ensuring that the required number of good dip-4s is seen. only then is a calendar provisioned. during periodic training, it is im portant to ensure that the traini ng result is no less accurate than that already used for the initial decision during power-on training. thus, a similar number of training cycles must be averaged over (32). this could make the ov erhead associated with periodic training large if it is required to be carried ou t too often. we therefore recommend that periodic training be scheduled infrequently (data_max_t = a large number) and that the number of repetitions of training be = 32( ). 3.2.4 fifo status channel fifo status information is sent periodically over the tstat link from the ixf1110 to the upper layer processor device, and over the rstat link from the upper layer processor to the ixf1110. the status channels operate independently. figure 12 shows the operation of the fifo status channel. the sending side of the fifo status channel is initially in the disable state and sends the ?1 1? pattern repeatedly. when fifo status transmission is enabled, there is a transition to the sync state and the ?1 1? framing pattern is sent. fifo status words are then sent according to the calendar sequence, repeating the sequence calendar_m times, followed by the dip-2 code.
intel ? ixf1110 10-port gigabit ethernet media access controller 44 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 the fifo status of each port is encoded in a 2-bit data structure, which is defined in table 11, ?fifo status format? on page 46 . the most significant bit of each port status is sent over tstat[1]/rstat[1] and the least significant bit is sent over tstat[0]/rstat[0]. the ?1 1? pattern is reserved for in-band framing, which mu st be sent once prior to the start of the fifo status sequence. immediately before the ?1 1? fram ing pattern, a dip-2 odd parity checksum is sent at the end of each complete sequence. the dip-2 code is comp uted diagonally over tstat[1]/rstat[1] and tstat[0]/rstat[0] for all preceding fifo status in dications sent after the last ?1 1? framing pattern, as shown in figure 13 on page 45 . the first word is at the top of the figure and the last word is at the bottom. the parity bits are computed by summing diagonally. bits a and b in line 9 correspond to the space occupied by the dip-2 parity bits and are set to 1 during encoding. the ?1 1? framing pattern is not included in the parity calculation. the procedure described applies to either parity generation on the egress path or to check parity on the ingress path. figure 12. fifo status state diagram port 4 port 3 port 2 port 1 port 0 port 9 port 8 port 7 port 6 port 5 sync 11 dip-2 en a b l e dis ab le 11 dis ab le
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 45 document #: 250210 revision #: 004 rev. date: december 18, 2002 when the parity bits mimic the ?1 1? pattern, th e receiving end still frames successfully by syncing onto the last cycle in a repeated ?1 1? pattern, and by making use of the configured sequence length when searching for the framing pattern. to permit more efficient fifo utilization, the maxburst1 and ma xburst2 credits are granted and consumed in increments of 16-byte blocks. for an y given port, these credits correspond to the most recently received fifo status. they are not cumulative and supersede previous ly granted credits for the given port. a burst transfer shorter than 16 bytes (for example, an end-of-packet fragment) consumes an entire 16-byte credit. a continuous stream of repeated ?1 1? framing patterns indicates a disabled status link. for example, it may be sent to indi cate that the data path de-skew is not yet completed or confirmed. when a repeated ?1 1? pattern is detected, a ll outstanding credits are cancelled and set to zero. figure 13. example of dip-2 encoding dip2 parity bits framing pattern (not included parity in calculations) 1st status word 2nd status word 3rd status word 4th status word 5th status word 6th status word 7th status word 8th status word dip2 parity bits (dip2[1:0]) a and b are set to 1 during enccoding 1 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 1 a b 2 3 4 5 6 7 8 9 to 2 to 3 to 4 to 5 to 6 to 7 to 8 to 9 1 0
intel ? ixf1110 10-port gigabit ethernet media access controller 46 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 the indicated fifo status is based on the latest available info rmation. a starving indication provides additional feedback inform ation, so that transfers are sc heduled accordingly. applications that do not distinguish between hungry and st arving may only examin e the most significant fifo status bit. note: if a port is disabled on the ixf1110, fifo status for the port is set to satisfied to avoid the possibility of any data being sent to it by th e controlling device. this applies to the ixf1110 transmit path. upon reset, the fifos in the data path receiver ar e emptied, and any outsta nding credits are cleared in the data path transmitter. after reset, and before active traffic is generated, the data transmitter sends continuous training patterns. transmission of the training patterns continues until valid information is received on the fifo status channel. the recei ver ignores all in coming data until it has observed the training pattern and acquired sync hronization with the data. synchronization may be declared after a provisional number of consecuti ve correct dip-4 code words is seen. loss of synchronization may be reported after a provisio nal number of consecutive dip-4 code words is detected. [for details, see table 86, ?spi4-2 tx synchronization register (addr: 0x703)? on page 142 .] as stated above, the dip-4 thresh olds are programmable. however, there is a potential issue where it is possible that a given link showing dip-4 errors may never lose synchronization and re-train to fix the issue. this would mean an on-going and potentially significant loss of data on the link affecting all ports transfer ring data at that time. this issue may be seen in two instances: ? during training (most likely periodic training) ? during data transfers where each of the data transfers (max burst1 or maxburst2) are separated by more than one idle control word table 11. fifo status format msb lsb description 1 1 reserved for framing or to indicate a disabled status link. 10 satisfied: indicates that the corresponding port' s fifo is almost full. when satisfied is received, only transfers using the remaining pr eviously granted 16-byte blocks (if any) may be sent to the corresponding port until the next st atus update. no additional transfers to that port are permitted while satisfied is indicated. 01 hungry: when hungry is received, transfers fo r up to maxburst2 16-byte blocks, or the remainder of what was previously granted (w hatever is greater), may be sent to the corresponding port until the next status update. 00 starving: indicates that buffer underflow is imminent in the corresponding phy port. when starving is received, transfers for up to maxburst1 16-byte blocks may be sent to the corresponding port until the next status update
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 47 document #: 250210 revision #: 004 rev. date: december 18, 2002 the mechanism for both issues is the same because data will not change during a repeated period of the same control word being transmitted on the link. if there have been some consecutive dip-4 errors, they will be incremented towards the loss- of-sync threshold. this is most likely to occur from a path requiring de-skew. if either a stream of idles or training control words follow the burst and the dip-4 associated with each of the words is checked, only th e first one and the last one will be seen as invalid. any other control words in th e middle will be seen as having a valid dip-4 and will reset the loss-of-sync threshold counter back to zero. in order to avoid this, the ixf1110 has altered the way in which the check is done for idle control words and training control words. we now only va lidate the first occurren ce of the dip-4 in both training control words a nd idle control word s for correctness. we do stil l check each of the words but only use the first occurrence to clear the dip-4 erro r counter. any dip-4 error in any of these words is still counted towards the loss-of-sync threshold counter. it is now impossible to mask the dip-4 error on our interface. 3.2.5 dc parameters for dc parameters on the spi4-2 interface, please refer to figure 23, ?2.5 v lvttl and cmos i/ o electrical characteristics? on page 78 and figure 24, ?lvds i/o elect rical characteristics? on page 78 . . 3.3 serdes interface 3.3.1 introduction the following sections describe the operati ons supported by each serdes interface, the configurable options, and register bits that control these options. (a full list of the register addresses and full bit definitions are found in the register map ( table 43, ?serdes block register map? on page 101 ). the ixf1110 includes ten serdes interfaces that allow direct co nnection to opti cal modules and remove the requirement for extern al serdes devices. this increases integration, which reduces the pcb real-estate, reduces both silicon and manufacturing cost s, and improves reliability. each serdes interface is identical and fully comp liant with the relevant ieee 802.3 specifications, including auto-negotiation. each po rt is also compliant with and su pports the requir ements of the sff committee gigabit interface converter (gbic) standards (sff-8053, revision 5.5). 3.3.2 features the serdes cores are designed to operate in point-to-point data transmission applications. while the core can be used across various media types, such as pcb or backplan es, it is configured specifically for use in 1000base-x ethernet fibe r applications in the ixf1110. the following features are supported. ? 10-bit data path, which connects to the output/input of the 8b/10b encoder/decoder pcs that resides in the mac controller ? data frequency of 1.25 ghz ? low power: <200 mw per serdes channel ? asynchronous clock data recovery
intel ? ixf1110 10-port gigabit ethernet media access controller 48 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 3.3.3 functional description 3.3.3.1 transmitter operational overview the transmit section of the ixf1110 has to seri alize the ten bit interface (tbi) data from the ixf1110 mac section and outputs this data at 1.25 ghz differential pecl signal levels. the 1.25 ghz differential pecl signal s are compliant with the sff- 8053 specification for gbic rev 5.5. the transmitter section takes the contents of the data register within the mac and synchronously transfers the data out, ten bits at a time ? least significant bit (lsb) first, followed by the next most significant bit (msb). when these ten bits have been serialized and transmitted, the next word of 10-bit data from the mac is ready to be serialized for transmission. the data is transmitted by the high-speed curren t mode differential pecl output stage using an internal 1.25 ghz clock generated from the 125 mhz clock input. 3.3.3.2 receiver operational overview the receiver structure performs clock and data recovery (cdr) on the incoming serial data stream. the quality of this oper ation is a dominant factor for th e bit error rate (ber) system performance. feed forward and f eedback controls are combined in one receiver architecture for enhanced performance. the data is over-sampled and a digital circuit detects the edge position in the data stream. a signal is not generated if an edge is not found. a feedback loop takes care of low-frequency jitter phenomenon of unlimited am plitude, while a feed fo rward section suppresses high-frequency jitter having limited amplitude. the static edge position is held at a constant position in the over-sampled by a constant adjustment of the sampling phases with the early and late signals. 3.4 gigabit interface converter 3.4.1 introduction this section describes the connection of the ixf111 0 ports to a gigabit interface converter (gbic) module, and the connections supported for correct operation are detailed. the registers used to write control and read status information are documented (refer to section 6.5.9, ?gbic block register overview? on page 144 ). the gbic interface allows the ixf1110 a seamless connection to the gbic modules that form the system?s physical media connection , eliminating the need for any fp gas or cpus to process data. all required information of the gbic modules is available to the system cpu via the ixf1110 cpu interface, leading to a more integrat ed, reliable, and cost-effective system. 3.4.2 gbic description gbics were originally designed for fiber channel applications using the fi ber channel arbitrated loop (fc-al). the design is practical for point-to-point fiber channel implementations and for other high-performance serial technologies, including 1000 mbps ethernet.
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 49 document #: 250210 revision #: 004 rev. date: december 18, 2002 there are specific mechanical and electrical requirements for the si ze, form factor, and connections supported on all gbics. there are also specifi c requirements for each gbic that supports a particular media requirement or interface configuration. these requirements are detailed in relevant specifications or manufacturers? datasheets. the ixf1110 supports all the functions required for full compatibility with gbic modules supporting the sff type 4 module (ref er to sff-8053, revision 5.5). figure 14 provides typical gbic module functionality. 3.4.3 ixf1110 supported gbic interface signals for gbic interface operation, thr ee supported signal subgroups ar e required, allowing a more explicit definition of each func tion and implementation. the th ree subgroups are as follows: ? high-speed serial interface ? low-speed status signaling interface ? i 2 c module configuration interface table 12 provides descriptions for ixf1110-to-gbic module connection pins. figure 14. typical gbic module functional diagram optical receiver laser amplifier los detect laser drive safety control mod_def power management and surge control internal interface 20-pin sca-2 connector to host gbic external fc port (example is duplex sc optical connector) pecl drive and termination +tx_data -rx_data rx_los - tx_data +rx_data tx_disable tx_fault mod_def(0) mod_def(1) mod_def(2) vddr vddt table 12. ixf1110-to-gbic connections ixf1110 pin names gbic module pin name description notes tx_9:0+ +tx_dat transmit data, differential pecl output from the ixf1110 tx_9:0- -tx_dat rx_9:0+ +rx_dat receive data, differential pecl input to the ixf1110 rx_9:0- -rx_dat
intel ? ixf1110 10-port gigabit ethernet media access controller 50 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 3.4.4 functional descriptions 3.4.4.1 high-speed serial interface these signals are responsible for transfer of th e actual data at 1.25 gbps. the data is 8b/10b encoded and transmitted differentially at pecl levels per the required specifications. this interface may be either ac or dc coupled (see table 43, ?serdes block register map? on page 101 ). the signals required to implement th e high-speed serial interface are: ? tx_9:0+ ? tx_9:0- ? rx_9:0+ ? rx_9:0- i 2 c_clk mod_def(1) i 2 c_clk output from ixf1110 (scl) output from the ixf1110 i 2 c_data_9:0 mod_def(2) i 2 c_data i/o (sda) input/output mod_def_9:0 mod_def(0) mod_def(0) should be ttl low level during normal operation. input to the ixf1110 tx_disable_9:0 tx_disable transmitter disable, logic high, open collector compatible output from the ixf1110 tx_fault_9:0 tx_fault transmitter fault, logic high, open collector compatible input to the ixf1110 rx_los_9:0 rx_los receiver loss of signal, logic high, open collector compatible input to the ixf1110 table 12. ixf1110-to-gbic connections (continued) ixf1110 pin names gbic module pin name description notes
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 51 document #: 250210 revision #: 004 rev. date: december 18, 2002 figure 15 shows a generic high-speed serial interface implementa tion (ac-coupled). note: the ixf1110 has integrated termination, thus all the components shown on the host board are not required. 3.4.4.2 low-speed status signaling interface the following low-speed sign als indicate the state of th e line via the gbic module: ? mod_def_9:0 ? tx_fault_9:0 ? rx_los_9:0 ? tx_disable_9:0 ? mod_def_int ? tx_fault_int ? rx_los_int 3.4.4.2.1 mod_def_9:0 these signals are direct inputs to the ixf1110 and are pulled to a logic low level during normal operation, indicating that a module is present for each channel, respectively. if a module is not present, a logic high is received, which is ach ieved by a pull-up resistor on the ixf1110 pad. figure 15. data path connection and termination 0.01 f (optional) 0.01 f (optional) 0.01 f (optional) 0.01 f (optional) 0.01 f 0.01 f bias 75 ? 75 ? 0.01 f pecl transmit data pecl receive data 0.01 f 0.01 f 0.01 f pecl receive data pecl transmit data gbic gbic connector host board 75 ? 75 ?
intel ? ixf1110 10-port gigabit ethernet media access controller 52 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 the status of each bit (one for each port) is found in bits 9:0 of the gbic status register (refer to table 90, ?gbic status register ports 0-9 (addr: 0x799)? on page 144 ). any change in the state of these bits causes a logic low level on the mod_def_int output if this operation is enabled. 3.4.4.2.2 tx_fault_9:0 these 10 pins are inputs to the ixf1110. these si gnals are pulled to a logic low level by the gbic module during normal operation, which indicates no fault condition exists. if a fault is present, a logic high is received via the use of a pull-up resistor on the ixf1110 pad. the status of each bit (one for each port) can be f ound in bits 19:10 of the gbic status register (see table 90, ?gbic status register ports 0-9 (addr: 0x799)? on page 144 ). any change in the state of these bits causes a logic low level on the tx_fault_int output if this operation is enabled. 3.4.4.2.3 rx_los_9:0 these 10 pins are inputs to the ixf1110. during normal operation, these signals are pulled to a logic low level by the gbic module, which indica tes that no loss-of-signal exists. if a loss-of- signal occurs, a logic high is received on these in puts via the use of a pull-up resistor on the ixf1110 pad. the status of each bit (one for each port) is found in gbic status register bits 29:20 (see table 90 on page 144 ). any change in the state of these bits causes a logic low level on the rx_los_int output if this operation is enabled. 3.4.4.2.4 tx_disable_9:0 these 10 pins are outputs from the ixf1110. during normal operation, these signals are pulled to a logic low level by the ixf1110, indicating that the gbic transmitter is enabled. if the gbic module transmitter is disabled, these signals are switched to a l ogic high level. on the ixf1110, these outputs are open-drain types and pulled up by the 4.7k to 10k pull-up resistor at the gbic module. each of these signals is controlled via gbic control regi ster bits 9:0, respectively (see table 91 on page 144 ). 3.4.4.2.5 mod_def_int mod_def_int is a single output, open-drain type signal, and is active low. a change in state of any of the mod_def_9:0 inputs cause s this signal to switch low and remain in this state until a read of the gbic status register takes place (see table 90 on page 144 ). the signal then returns to an inactive state. note: the mod_def_9:0 inputs shown in table 90, ?gbic status register ports 0-9 (addr: 0x799)? on page 144 are synchronized with an inte rnal system clock. this results in a delay from the time the signal is active to the register bit and/or interrupt being set. 3.4.4.2.6 tx_fault_int tx_fault_int is a single output, open-drain type si gnal, and is active low. a change in state of any of the tx_fault_9:0 inputs causes this signal to switch low and remain in this state until a read of the gbic status register takes place (see table 90 on page 144 ). the signal then returns to an inactive state.
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 53 document #: 250210 revision #: 004 rev. date: december 18, 2002 note: the tx_fault_9:0 inputs shown in table 90, ?gbic status register ports 0-9 (addr: 0x799)? on page 144 are synchronized with an internal system clock. this results in a delay from the time the signal is active to the register bit and/or interrupt being set. 3.4.4.2.7 rx_los_int rx_los_int is a single output, open- drain type signal, and is active low. a change in state of any of the rx_los_9:0 inputs causes this signal to switch low and remain in this state until a read of the gbic status register has taken place. th e signal then returns to an inactive state. note: the rx_los_9:0 inputs shown in table 90, ?gbic status register ports 0-9 (addr: 0x799)? on page 144 are synchronized with an inte rnal system clock. this result s in a delay from the time the signal is active to the register bit and/or interrupt being set. note: mod_def_int, tx_fault_int, and rx_los_int are open-drain type outputs. with the three signals on the device, the system can decide which gbic status register bits to look at to identify the interrupt condition source port. however, this is achieved at the expense of two device pins. in systems that cannot support multiple interrupt signals (applications that do not have extra hardware pins), these three outputs can be connect ed to a single pull-up resistor and used as a single interrupt pin. 3.4.5 i 2 c module configuration interface the i 2 c interface is supported on type 4 sff gbic modu les. details of the operation are found in sff-8053, revision 5.5, annex d, module defi nition ?4? gbic (serial identification). this document details the contents of the register s and addresses accessible on a given gbic module supporting this interface. sff-8053 identifies up to 512 8-bit registers that are accessible in each gbic. the gbic interface is read/write capable and supports either sequen tial or random access to the 8-bit parameters. the maximum clock rate of the inte rface is 100 khz. all address select pins on the internal e 2 prom are tied low to give a device address equal to zero (00h). the specific interface in the ixf1110 supports only a subset of the full i 2 c interface, and only the features required to support the gbic modules are implemented, leading to the following support features: ? single i 2 c_clk pin connected to all gbic modules , and implemented to save unnecessary pin use. ? ten per-port i 2 c_data pins (i 2 c_data_9:0) are required due to the gbic module requirement that all modules must be addressed as 00h. ? due to the single internal gbic controller, only one gbic module may be accessed at any one time. fiber gbic accesses contains a single regi ster read. since these register accesses will most likely be done during power-up or discove ry of a new module, these restrictions should not affect normal operation. ? the i 2 c interface also supports byte write accesses to the full address range.
intel ? ixf1110 10-port gigabit ethernet media access controller 54 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 3.4.5.1 general description in the ixf1110, the entire i 2 c interface is controlled through separate i 2 c control and data registers (see table 93 on page 146 ). the general operation is described below. the i 2 c control register is divided into the following sections: ? port address error ? write protect error bit ? no acknowledge error bit ? i 2 c enable bit ? i 2 c start access bit ? write access complete bit ? read datavalid bit ? 4-bit port address select ? read/write access select ? 4-bit device id ? 11-bit register address the i 2 c data register is divided into the following sections: ? 8-bit write data ? 8-bit read data the 4-bit device id field defaults to ah, this valu e is compatible with standard fiber gbic based on the atmel serial e 2 prom family. i 2 c accesses to non-atmel compatib le devices will require to update this field with the appropriate value. the 11-bit register address is split into two sub-fields: ? bits [10:8] must be set to 0h to be compatible with standard fiber gbic. alternatively these bits can be set to 1h - 7h to permit access to seven other i 2 c component on the same bus. ? bits [7:0] specify the particul ar location to be accessed with in the device specified by the device id field and re gister address[10:8]. initiating an access where the 4-b it port address field to a value > 9h will not generate an i 2 c access. instead the port ad dress error will be set. initiating a write access where the device id field = ah and the register address[10:8] = 0h will generate an i 2 c access. in addition the write protect erro r bit will be set to indicate a write has been initiated to the wr ite protected fiber gbic.
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 55 document #: 250210 revision #: 004 rev. date: december 18, 2002 3.4.5.1.1 read access operation example read the data stored at port 5 (port addre ss select), register 00 0h (data address select). 1. program the ?i2c data register ports 9-0 register (addr: 0x79c)? with the following information: a. enable i 2 c block by setting bit 25 to ?1?. b. set the port to be accessed by setting bits [19:16] to 5h. c. select a read access by setting bit 15 to ?1?. d. set the device id, bits [14:11] to be ah (atmel compatible). e. set the 11-bit register address, bits [10:0] to 000h. f. initiate the i 2 c transfer by setting bit 24 to ?1?. all other bits in this register should be written with the value ?0?. this data is written into the i 2 c control register in a sing le cycle via the cpu interface. 2. when this register is written and the i 2 c start bit is at a logic 1, the i 2 c access state machine examines the port address select and enables the i 2 c_data_0:9 output for the selected port. 3. the state machine uses the data in the device id and register ad dress fields to build the data frame to be sent to the gbic. 4. the i 2 c data_read_fsm internal st ate machine takes over the task of transferring the actual data between the ixf1110 and the se lected gbic (refer to the details in section 3.4.5.2, ?i2c protocol specifics? on page 56 ). 5. the i 2 c data_read_fsm internal state machine places the received data into the read_data field, bits [7:0] of the i 2 c data register, and sets the read data valid bit, bit 20 of the i 2 c control register to ?1? to signify that the read data is valid. 6. the data is read through the cpu interface. the cpu must poll the read da ta valid bit until it is set to ?1. only once this bit is set, it is safe to read the data in the i 2 c data register.
intel ? ixf1110 10-port gigabit ethernet media access controller 56 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 3.4.5.1.2 write access operation example write the data to port 9 (port address sel ect), register 0ffh (data address select). 1. program the ?i2c data register ports 9-0 register (addr: 0x79c)? with the following information: a. enable i 2 c block by setting bit 25 to ?1?. b. set the port to be accessed by setting bits [19:16] to 5h. c. select a write access by setting bit 15 to ?0?. d. set the device id, bits [14:11] to be ah (atmel compatible). e. set the 11-bit register address, bits [10:0] to 0ffh. f. initiate the i 2 c transfer by setting bit 24 to ?1?. all other bits in this register should be written with the value ?0?. this data is written into the i 2 c control register in a single cycle via the cpu interface. 2. when this register is written and the i 2 c start bit is at a logic 1, the i 2 c access state machine examines the port address select and enables the i 2 c_data_0:9 output for the selected port. 3. the state machine uses the data in the device id and register address fields to build the data frame to be sent to the gbic. 4. the i 2 c data_write_fsm internal state machine takes over the task of transferring the actual data between the ixf1110 and the se lected gbic (refer to the details in section 3.4.5.2, ?i2c protocol specifics? on page 56 ). 5. the i 2 c data_write_fsm internal state machine uses the data from the write_data field, bits [23:16] of the i 2 c data register, and sets the write_complete bit, bit 22 of the i 2 c control register to ?1? to signify that the write access is complete. 6. the data is written through the cpu interface. the cpu must poll the write_complete bit until it is set to ?1. only once this bit is set, it is safe to request a new access. note: only one gbic i 2 c access sequence can be run at any given time. if a second write is carried out to the i 2 c control register before a result is returned for the previous write, the data for the first write is lost. to ensure no data is lost, make sure write complete = 1 before starting the next write sequence. 3.4.5.2 i 2 c protocol specifics this section describes the i 2 c protocol behavior supported by the ixf1110, which is controlled by an internal state machine. specifi c protocol states are defined below, with an additional description of the hardware pins used on the interface. the serial clock line (i 2 c_clk) is an ixf1110 output. the serial data is synchronous with this clock and is driven off the rising edge by the ixf1110 and off the falling edge by the gbic module. the ixf1110 has only one i 2 c_clk line that drives al l of the gbic modules. i 2 c_clk runs continuously when enabled (i 2 c enable = 01h0). the serial data (i 2 c_data_0:9) pins (one per port) are bi-d irectional for serial data transfer, and are open drain.
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 57 document #: 250210 revision #: 004 rev. date: december 18, 2002 3.4.5.3 port protocol operation 3.4.5.4 clock and data transitions the i 2 c_data is normally pulled high with an extra device. data on the i 2 c_data pin changes only during the i 2 c_clk low time periods (see figure 16 ). data changes during i 2 c_clk high periods indicate a start or stop condition. 3.4.5.4.1 start condition a high-to-low transition of i 2 c_data, with i 2 c_clk high, is a start condition that must precede any other command (see figure 17 ). 3.4.5.4.2 stop condition a low-to-high transition of the i 2 c_data with i 2 c_clk high is a stop condition. after a read sequence, the stop command places the e 2 prom in the gbic in a standby power mode (see figure 17 ). figure 16. data validity timing diagram data stable data stable data change i 2 c_data i 2 c_clk figure 17. start and stop definition timing diagram start stop i 2 c_data i 2 c_clk
intel ? ixf1110 10-port gigabit ethernet media access controller 58 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 3.4.5.4.3 acknowledge all addresses and data words are serially transmitted to and from the gbic in 8-bit words. the gbic e 2 prom sends a zero to acknowledge that it ha s received each word, which happens during the ninth clock cycle (see figure 18 ). 3.4.5.4.4 memory reset after an interruption in protocol, power loss, or system reset, any two-wire gbic can be reset by following three steps: 1. clock up to 9 cycles 2. wait for i 2 c_data high in each cycle while i 2 c_clk is high 3. initiate a start condition memory reset on this device is defined as follows: always add a stop condition following the start as there is no clean finish to end the reset of the memory with a start condition after completing steps one through three. this ensures a clean protocol termination if there is no more data to transfer at the end of the reset cycle. 3.4.5.4.5 device addressing all e 2 proms in gbic devices require an 8-bit devi ce address word following a start condition to enable the chip to read or wr ite. the device address word co nsists of a mandatory one, zero sequence for the four most significant bits. this is common to all devices. the next 3 bits are the a2, a1 and a0 device address bits that are tied to zero in a gb ic module. the eighth bit of the device address is the read/write operation select b it. a read operation is initiated if this bit is high and a write operation is initiated if this bit is low. upon comparison of the device address, the gbic module outputs a zero. if a comparison is not made, the gbic e 2 prom returns to a standby state. when not accessing the gbic e 2 prom, the device address or device id is completely programmable for maximum flexibility. figure 18. acknowledge timing diagram start acknowledge i 2 c_data data in data out
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 59 document #: 250210 revision #: 004 rev. date: december 18, 2002 3.4.5.4.6 random read operation a random read requires a ?dummy? byte/write se quence to load the data word address. the following describes how to achieve the ?dummy? write: ? the ixf1110 generates a start condition. ? the ixf1110 sends a device address word with th e read/write bit cleared to low, signaling a write operation. ? the gbic acknowledges receipt of the device address word. ? the ixf1110 sends the data word address, which is again acknowledged by the gbic. ? the ixf1110 generates another start condition. this completes the ?dummy? write and sets the gbic e 2 prom pointers to the desired location. the following describes how the ixf11 10 initiates a current address read: ? the ixf1110 sends a device address with the read/write bit set high ? the gbic acknowledges the device address an d serially clocks out the data word. ? the ixf1110 does not respond with a zero but generates a stop condition (see figure 19 ). timing diagrams and tables can be found in section 5.0, ?test specifications? on page 77 . 3.4.5.4.7 byte write operation the following describes how to achieve the byte write operation: ? the ixf1110 generates a start condition. ? the ixf1110 sends a device address word with th e read/write bit cleared to low, signaling a write operation. ? the gbic acknowledges receipt of the device address word. ? the ixf1110 sends the data word address. ? the gbic acknowledges receipt of the data word address. ? the ixf1110 sends the data byte to be written. ? the gbic acknowledges the data word. figure 19. random read device address device address word address sda line dummy write (* = don't care bit for 1k) start s t a r t r e a d s t a r t w r i t e s t o p m s b m s b m s b l s b r / w l s b data n l s b a c k n o a c k a c k
intel ? ixf1110 10-port gigabit ethernet media access controller 60 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 ? the ixf1110 generates a stop condition (see figure 20 ). 3.4.5.5 ac timing characteristics table 35, ?i2c ac timing characteristics? on page 90 , figure 39, ?i2c bus timing diagram? on page 90 , and figure 40, ?i2c write cycle diagram? on page 90 provide the ac timing characteristics of the gbic interface. 3.5 led interface 3.5.1 introduction the ixf1110 uses a serial interf ace consisting of three signals to provide led data to some form of external driver. this interface provides the da ta for 30 separate direct drive leds and allows three leds per mac port. there are two modes of operation, each with its own separate le d decode mapping. modes of operation and leds are detailed in ?modes of operation? . 3.5.2 modes of operation mode selection is accomplished by using the led_se l_mode bit. th is bit is globally selected and controls the operation of all ports (see table 68, ?led control register (addr: 0x509)? on page 120 ). there are two modes of operation: mode 0: (led_sel_mo de = 0 [default]): this mode selects operat ions compatible with the sgs thompson m5450 led display driver device. this device converts th e serial data stream, output by the ixf1110, into 30 direct-drive led outputs. mode 1: (led_sel_mode = 1): this mode is used with st andard ttl (74ls595) or hcmos (74hc595) octal shift registers with latches, providing the most general and cost-effective implementation of the serial data stream conversion. figure 20. byte write device address word address i 2 c_data line (* = don't care bit for 1k) s t a r t w r i t e m s b m s b l s b r / w l s b a c k * a c k s t o p data n a c k a c k
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 61 document #: 250210 revision #: 004 rev. date: december 18, 2002 in addition to these physical modes of operation, there are two types of specific led data decodes available. this option is a global selection and controls the operation of all ports (see table 68, ?led control register (addr: 0x509)? on page 120 ). 3.5.3 led interface signal description the ixf1110 led interface consists of three output signal pins that are 2.5 v cmos level pads. table 13 provides led signal names, pin numbers and descriptions. 3.5.4 mode 0: detailed operation note: please refer to the sgs thompson m5450 da tasheet for device-op eration information. the operation of the led interface in mode 0 is based on a 36-bit counter loop. the data for each led is placed in turn on th e serial data line and clocked out by the led_clk. figure 21 on page 61 shows the basic timing relationship and relative positioning in the data stream of each bit. figure 21 shows the 36 clocks that are output on the led_clk pin. the data changes on the falling edge of the clock and is valid for almost the entire clock cycle. this ensures that the data is valid during the rising edge of the led_clk, which is used to clock the data into the m5450 device.the actual data shown in figure 21 consists of a chain of 36 bits only, 30 of which are valid led data. the 36-bit data chain is built up as follows: table 13. led pin descriptions pin name pin # pin description led_clk a20 led_clk: this signal is an output that provides a continuous clock synchronous to the serial data stream output on th e led_data pin. this clock has a maximum speed of 0.5 mhz. the behavior of this signal remains constant in all modes of operation. led_data a19 led_data: this signal provides the data, in various formats, as a serial bit stream. the data must be valid on the rising edge of the led_clk signal. in mode 0, the data presented on this pin is true (logic 1 = high). in mode 1, the data presented on this pin is inverted (logic 1 = low). led_latch k18 led_latch: this is an output pin and the signal is used only in mode 1 as the latch enable for the shift register chain. this signal is not used in mode 0, and should be left unconnected. figure 21. mode 0 timing diagram 1 23 24 25 26 27 28 29 30 135 26 234 led_clk led_data led_latch 34 27 33 32 31 30 29 28 36
intel ? ixf1110 10-port gigabit ethernet media access controller 62 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 when implemented on a board with the m5450 devi ce, the led data bit 1 appears on output bit 3 of the m5450 and the led data bit 2 appears on output bit 4, etc. this means that output bits 1, 2, 3, 34, and 35 will never have valid data and should not be used. 3.5.5 mode 1: detailed operation note: please refer to manufacturers? 74ls/hc595 datasheet for information on device operation. the operation of the led interface in mode 1 is again based on a 36 -bit counter loop. the data for each led is placed in turn on the serial da ta line and clocked out by the led_clk. figure 22 on page 63 shows the basic timing relationship and relativ e positioning in the da ta stream of each bit. figure 22 shows the 36 clocks that are output on the led_clk pin. the data changes on the falling edge of the clock and is valid for almost the entire clock cycle. this ensures that the data is valid during the rising edge of the led_clk, wh ich is used to clock the data into the shift register chain devices. the led_latch signal is required in mode 1, and is used to latch the data shifted into the shift register chain into the output latches of the 74hc595 device. as seen in figure 22 , the led_latch signal is active high during the low period on the 36th led_clk cycle. this avoids any possibility of trying to latch data as it is shifting through the register. table 14. mode 0 clock cycle to data bit relationship led_clk cycle led_data name led_data description 1start bit this bit is used to synchronize the m5450 device to expect 35 bits of data to follow. 2:3 pad bits these bits are used only as fillers in the data stream to extend the length from the actual 30 bit led data to the required 36-bit frame length. these bits should always be a logic 0. 4:33 led data 1-30 these bits are the actual data transmitted to th e m5450 device. the decode for each individual bit in each mode is defined in table 13 on page 61 . the data is true. logic 1(led on) = high 34:36 pad bits these bits are used as fillers in the data stream to extend the length from the actual 30-bit led data to the required 36-bit frame length. these bits should always be a logic 0.
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 63 document #: 250210 revision #: 004 rev. date: december 18, 2002 when this operation mode is im plemented on a board with a shif t register chain containing three 74hc595 devices, the led data bit 1 is output on shift register bit 1, and so on up the chain. only shift register bits 31 and 32 do not contain valid data. the actual data shown in figure 22 consists of a 36-bit chain, of which 30 bits are valid led data. the 36-bit data chain is built up as follows: note: the led_data signal is now invert ed from the state in mode 0. 3.5.6 power-on, reset, and initialization the led interface is disabled at power-on or reset. the system software co ntroller must enable the led interface. the internal state m achines and output pins are held in reset until the full ixf1110 device configuration is completed. this is done by setting the led_enable bit to a logic 1 (see table 68, ?led control register (addr: 0x509)? on page 120 ). the power-on default for this bit is logic 0. 3.5.7 led data decodes table 16 shows the data decode of the data for the ixf1110. figure 22. mode 1 timing diagram table 15. mode 1 clock cycl e to data bit relationship led_clk cycle led_data name led_data description 1start bit this bit has no meaning in mode 1 operation and is shifted out of the 32-stage shift register chain before the led_latch signal is asserted. 2:3 pad bits these bits have no meaning in mode 1 operation and are shifted out of the 32-stage shift register chai n before the led_latch signal is asserted. 4:33 led data 1-30 these bits are the actual data to be transmitted to the 32-stage shift register chain. the decode for each bit in each mode is defined in table 15 on page 63 . the data is inverted. logic 1 (led on) = low. 34:36 pad bits these bits have no meaning in mode 1 operation and are latched into positions 31 and 32 in th e shift register chain. these bits are not considered as valid data and should be ignored. they should always be a logic 0 = high. 1 23 24 25 26 27 28 29 30 135 234 led_clk led_data led_latch 33 32 31 30 29 28 27 26 34 36
intel ? ixf1110 10-port gigabit ethernet media access controller 64 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 3.5.7.1 led signaling behavior operation in each mode for the decoded led data in table 16 is detailed in table 17 . 3.5.7.1.1 ixf1110 led behavior table 16. led data decodes led_data# macport # ixf1110 designation 1 0 rx led - amber 2 rx led - green 3 tx led - green 4 1 rx led - amber 5 rx led - green 6 tx led - green 7 2 rx led - amber 8 rx led - green 9 tx led - green 10 3 rx led - amber 11 rx led - green 12 tx led - green 13 4 rx led - amber 14 rx led - green 15 tx led - green 16 5 rx led - amber 17 rx led - green 18 tx led - green 19 6 rx led - amber 20 rx led - green 21 tx led - green 22 7 rx led - amber 23 rx led - green 24 tx led - green 25 8 rx led - amber 26 rx led - green 27 tx led - green 28 9 rx led - amber 29 rx led - green 30 tx led - green
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 65 document #: 250210 revision #: 004 rev. date: december 18, 2002 3.6 cpu interface 3.6.1 general description the cpu interface block provides access to registers a nd statistics in the ix f1110. the interface is asynchronous externally and operates within th e 125 mhz clock domain internally. the interface provides access to the following registers: ? mac control ? mac rx statistics ? mac tx statistics ? global status and configuration ? rx block ? tx block ? spi4-2 block ? serdes block ? gbic block 3.6.2 functional description 3.6.2.1 read access read access involves the following: ? detect assertion of asynchronous read control signal and latch address ? generate internal read strobe ? drive valid data onto processor bus ? assert asynchronous-ready signal for required length of time table 17. ixf1110 led behavior type status description rxled amber off port has no link synchronization or remote fault error on port has a link synchronization error or no optical signal blinking port has remote fault rxled green off port is not enabled on port has link and is enabled blinking port is receiving data txled green off port is not transmitting data blinking port is transmitting data
intel ? ixf1110 10-port gigabit ethernet media access controller 66 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 figure 23 provides the timing of the asynchronous interface for read access. 3.6.2.2 write access the write process invo lves the following: ? detect assertion of asynchronous wr ite control signal and latch address ? detect de-assertion of asynchronous write control signal and latch data ? generate internal write strobe ? assert asynchronous ready signal for required length of time figure 24 illustrates the timing of the as ynchronous interface for write access. figure 23. read timing diagram - asynchronous interface t cas t cah t crr t cdrs t cdrh t cdrd t crh upx_add[10:0] upx_rd upx_cs upx_data[31:0] upx_rdy figure 24. write timing diagram - asynchronous interface t cas t cah t cwl t cdws t cdwd t cyd t cwh upx_add[10:0] upx_wr upx_cs upx_data[31:0] upx_rdy t cdwh
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 67 document #: 250210 revision #: 004 rev. date: december 18, 2002 3.6.3 endian the endian of the cpu interface may be changed to allow co nnection of various cpus to the ixf1110. the endian selection is determined by setting the endian bit in the cpu interface register (see table 67 on page 120 ). 3.7 clocks the ixf1110 device has system interface reference clocks, spi4-2 data path input and output clocks, a jtag input clock, a gbic output clock, and an led output clock. this section details the unique clock source requirements. 3.7.1 system interf ace reference clocks there are two system interface clocks required by the ixf1110: 3.7.1.1 clk125 the system interface clock, which su pplies the clock to the majority of the internal circuitry, is the 125 mhz clock. the source of this clock must meet the following specifications: ? 2.5 v cmos drive ? +/- 50 ppm ? maximum duty cycle distortion 40/60 3.7.1.2 clk50 the other system interface clock su pplies the clock source to the spi4-2 receive circuitry. the source of this clock must meet the following specifications: ? 2.5 v cmos drive ? 1/8 frequency of the spi4-2 data path clock (rdclk+/-) ? maximum duty cycle distortion 45/55 ? maximum peak-to-peak jitter (low and high frequency) of 125 ps ? range = 40 mhz to 50 mhz 3.7.2 spi4-2 receive and tran smit data path clocks the spi4-2 data path clocks are compliant with the oif 2000.88.4 specification. the ixf1110 has the following requirements on the transmit data path: ? 2.5 v lvds drive ? maximum duty cycle distortion 45/55 ? maximum peak-to-peak jitter (low and high frequency) of 125 ps ? stable (frequency and level) when reset is removed or when sourced, whichever happens last
intel ? ixf1110 10-port gigabit ethernet media access controller 68 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 ? tsclk frequency is one-quarter tdclk frequency the ixf1110 meets the foll owing specifications on the receive data path: ? 2.5 v lvds drive ? maximum duty cycle distortion 45/55 ? maximum peak-to-peak jitter (low and high frequency) of 125 ps ? stable when sourced 3.7.3 jtag clock the ixf1110 supports jtag. the source of this clock must meet the following specifications: ? 2.5 v cmos drive ? maximum clock frequency 11 mhz ? maximum duty cycle distortion 40/60 3.7.4 gbic clock the ixf1110 device supports a single output gbic clock to support all 10 gbic interfaces. the ixf1110 meets the following sp ecifications for this clock: ? 2.5 v cmos drive ? maximum clock frequency of 100 mhz 3.7.5 led clock the ixf1110 supports a serial led data stream. this interface implements a 2.5 v cmos output clock with a maximum frequency of 720 khz. the ixf1110 supports a serial led data stream. the ixf1110 meets the following specifications for this clock: ? 2.5 v cmos drive ? maximum frequency of 720 khz ? maximum duty cycle distortion: 50/50
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 69 document #: 250210 revision #: 004 rev. date: december 18, 2002 4.0 applications 4.1 tx and rx fifo operation the intel ? ixf1110 packet buffering is comprised of individual port fifo s and system-interface fifos. figure 25 illustrates the interaction of these fifos. 4.1.1 tx fifo the ixf1110 tx fifos are implem ented with 4.5 kb for each ch annel. this pr ovides enough space for at least one maximum size packet pe r-port storage and ensures that no under-run conditions occur, assuming that the sending devi ce can supply data at the required data rate. the mac threshold parameter, which is user prog rammable, determines when data is transmitted out of the mac. this parameter is configurable for specific block sizes and the user must ensure that an under-run does not occur. the threshold mu st be set to a value th at exceeds the programmed maxburst1 parameter. this method of operation el iminates the possibility of under-run, except when the controlling switch device fails. figure 25. packet buffering fifo mdi high water mark data flow mac transfer threshold * low water mark high water mark data flow low water mark rx fifo high txpausefr (external 802.3x pause frame generation strobe) tx fifo tx side mac rx fifo 802.3 flow control rx side mac spi4-2 interface 1. note: the mac transfer threshold determines when the transmit data is transferred from the tx fifo to the tx side of the mac. once the data has b een sent from the tx fifo to the mac, it will be transmitted to the phy and cannot be flow controlled from the link partner.
intel ? ixf1110 10-port gigabit ethernet media access controller 70 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 4.1.2 rx fifo the ixf1110 rx fifos are provisio ned so that each port has its ow n 17.0 kb memory space. this is enough memory to ensure agai nst an over-run on any channel while transferring normal ethernet frame-size data. the fifos can be configured to automatically generate pause control frames to initiate the following: ? halt the link partner when th e high watermark is reached ? restart the link partner when the data stored in the fifo falls below the low watermark 4.2 reset and initialization when powering up the ixf1110, the hardware reset signal (sys_res ) should be held active low for a minimum of 100 ns after all of the power rails have fully stabilized to their nominal values and the input clocks have reached their nominal frequency (tdclk = 400 mhz, clk125 = 125 mhz, and clk50 = 50 mhz). note: in systems where the sys_res pin is driven from a single board-wide reset signal, the switch or network processor only comes out of reset at the same time as the ixf1110, or possibly later. this means the tdclk will not be stable when the sys_res pin is released. a bu ilt-in feature in the ixf1110 reactivates the internal reset once tdclk is applied. ensu re that the switch or network processor does not output tdclk until it is stable and has reached its nominal operating frequency. the ixf1110 extends this hardware reset internally to ensure synchronization of all internal blocks within the system. the internal reset is extended for a minimum of 4.11 ms after all clocks are stable. the device is correctly initialized at this point and ready for use. clocks start to appear at the relevant device ports and the spi4-2 interface begins to s ource a training pattern on the receive side while waiting for a training patter n on the transmit side. the spi4- 2 interface synchr onizes with the connected switch or network proces sor per the spi4-2 specification. the cpu accesses can begin to configure the devi ce for any existing user preferences desired. by default, all ports on the ixf1110 are enabled afte r power-up. the device is ready for use at this time if the default settings are to be used. ot herwise, access the required registers via the cpu interface and configure the control re gisters to the required settings. 4.3 optical module conn ections to the ixf1110 4.3.1 sfp-to-ixf1110 connection the ixf1110 serdes and gbic interfaces allow system designers to connect the ixf1110 to various optical transceivers. when using small fo rm factor pluggable (sfp ) optical transceivers to connect to the ixf1110, all serdes and gbic status pins are used. use figure 26 and table 18 to connect an sfp to the ixf1110.
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 71 document #: 250210 revision #: 004 rev. date: december 18, 2002 figure 26. sfp-to-ixf1110 connection diagram table 18. sfp-to-ixf1110 connection sfp pin # sfp pin name ixf1110 pin # 0:9 ixf1110 pin name description 1 veet na na connect to ground. 2 txfault m24, v23, y17, r15, w14, w11, w9, ac5, p8, l2 tx_fault_[0:9] use an external 4.7 k ? pull-up resistor to 3.3 v. 3 txdisable k22, m22, ac22, u18, u14, aa18, u9, aa9, v7, l4 tx_disable_[0:9] sfp modul e has internal pull-up. 4 mod_def (2) g22, g23, j24, f22, e23, h24, g20, e22, g24, f24 i 2 c_data_[0:9] use an external 4.7 k ? pull-up resistor to 3.3 v. 5 mod_def (1) l19 i 2 c_clk use an external 4.7 k ? pull-up resistor to 3.3 v. 6 mod_def (0) n24, y21, aa16, m20, ac14, u11, t4, ab2, r7, l1 mod_def_[0:9] use an external 4.7 k ? pull-up resistor to 3.3 v. 7 rate select na na leave floating. 8los l22, v17, ad18, r12, ab15, v12, y9, ac3, t2, p2 rx_los_[0:9] use an external 4.7 k ? pull-up resistor to 3.3 v. 9 veer na na connect to ground. 10 veer na na connect to ground. 11 veer na na connect to ground. tx_fault tx_disable tx+ tx- rx+ rx- i 2 c_data i 2 c_clk mod_def rx_los txfault txdisable td+ td- rd- rd+ mod_def(0) los mod_def(2) mod_def(1) rate_select veer 14 vccr 15 veer 9 veer 11 veer 10 vcct 16 veet 1 veet 17 veet 20 4.7 k ? ixf1110 sfp vdd 3.3 v vdd 3.3 v tx_fault_int rx_los_int mod_def_int external cpu 2 4 5 6 3 8 18 19 12 13 7 4.7 k ? vdd 3.3 v 4.7 k ? 4.7 k ? 4.7 k ? 4.7 k ?
intel ? ixf1110 10-port gigabit ethernet media access controller 72 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 12 rd- u22, u20, t24, v24, ab14, ad14, ac16, ad15, v4, y5 rx-_[0:9] the ixf1110 has a 100 ? differential termination on the chip that requires it to be ac-coupled. ac-coupling is done inside the sfp module and is not required on the host board. 13 rd+ t22, t20, u24, w24, ab13, ad13, ab16, ad16, v5, y6 rx+_[0:9] 14 veer na na connect to ground. 15 vccr na na connect to filtered 3.3 v. 16 vcct na na connect to filtered 3.3 v. 17 veet na na connect to ground. 18 td+ v20, y19, v22, y23, ab12, ad12, ab9, ad9, t3, t5 tx+_[0:9] these pins are the differential transmitter inputs. they are ac-coupled differential lines with 100 ? differential termination inside the sfp module. the ac-coupling is done inside the sfp module and is not required on the host board. 19 td- v21, y20, w22, y22, ab11, ad11, ac9, ad10, u3, u5 tx-_[0:9] 20 veet na na connect to ground. n/a n/a b11 tx_fault_int connect to interrupt service routine. use an external 4.7 k ? pull-up resistor to 3.3 v. n/a n/a b14 rx_los_int connect to interrupt service routine. use an external 4.7 k ? pull-up resistor to 3.3 v. n/a n/a g15 mod_def_int connect to interrupt service routine. use an external 4.7 k ? pull-up resistor to 3.3 v. table 18. sfp-to-ixf1110 connection (continued) sfp pin # sfp pin name ixf1110 pin # 0:9 ixf1110 pin name description
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 73 document #: 250210 revision #: 004 rev. date: december 18, 2002 4.3.2 sff-to-ixf1110 connection use figure 27 and table 19 to connect a small form factor (sff) optical transceiver to the ixf1110. figure 27. sff-to-ixf1110 connection diagram table 19. sff-to-ixf1110 connection sff pin # sff pin name ixf1110 pin # 0:9 ixf1110 pin name description 1 veet na na connect to ground. 2 vccr na na connect to 3.3 v. 3sd l1, r7,ab2, t4, u11, ac14, m20, aa16, y21, n24 mod_def[0:9] need to invert sd or force the ixf1110 to be permanently enabled by connecting mod_def[0:9] directly to ground. 4 rd- y5, v4, ad15, ac16, ad14, ab14, v24, t24, u20, u22 rx -_[0:9] the ixf1110 has a 100 ? differential termination on the chip and requires ac-coupling. 5 rd+ y6, v5, ad16, ab16, ad13, ab13, w24, u24, t20, t22 rx +_[0:9] 6 vcct na na connect to 3.3 v. 7 veet na na connect to ground. 8txdis l22, v17, ad18, r12, ab15, v12, y9, ac3, t2, p2 tx_disable[0:9] need to invert tx_disable or force sff to be permanently enabled by connecting txdis directly to ground. tx_fault tx_disable tx+ tx- rx+ rx- i 2 c_data i 2 c_clk mod_def rx_los 8 txdis 9 td+ 10 td- 5 rd+ 4 vrd- 3 sd vccr 2 veer 1 vcct 6 veet 7 4.7 k ? ixf1110 serdes and gbic interfaces sff module vdd 3.3 v tx_fault_int rx_los_int mod_def_int 4.7 k ? 4.7 k ? 4.7 k ?
intel ? ixf1110 10-port gigabit ethernet media access controller 74 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 9td+ t5, t3, ad9, ab9, ad12, ab12, y23, v22, y19, v20 tx +_[0:9] the sff has a 100 ? differential termination inside the module. the ixf1110 requires these to be ac-coupled. 10 td- u5, u3, ad10, ac9,ad11, ab11, y22, w22, y20, v21 tx -_[0:9] various ms n/a n/a chassis ground connection (may vary from manufacturer to manufacturer). n/a n/a m24, v23, y17, r15, w14, w11, w9, ac5, p8, l2 tx_fault[0:9] use external 4.7 k ? pull-down to ground to ensure proper operation. n/a n/a l22, v17, ad18, r12, ab15, v12, y9, ac3, t2, p2 rx_los_[0:9] use external 4.7 k ? pull-down to ground to ensure proper operation. n/a n/a g22, g23, j24, f22, e23, h24, g20, e22, g24, f24 i 2 c_data_[0:9] leave as no-connect. n/a n/a l19 i 2 c_clk leave as no-connect. n/a n/a b11 tx_fault_int leave as no-connect. n/a n/a b14 rx_los_int leave as no-connect. n/a n/a g15 mod_def_int leave as no-connect. table 19. sff-to-ixf1110 connection (continued) sff pin # sff pin name ixf1110 pin # 0:9 ixf1110 pin name description
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 75 document #: 250210 revision #: 004 rev. date: december 18, 2002 4.3.3 1 x 9-to-ixf1110 connection use figure 28 and table 20 to connect a 1 x 9 optical transceiver to the ixf1110. figure 28. 1 x 9-to-ixf1110 connection table 20. 1 x 9-to-ixf1110 connection 1 x 9 pin # 1x9 pin name ixf1110 pin # 0:9 ixf1110 pin name description 1 veer na na connect to ground. 2 rd+ y6, v5, ad16, ab16,ad13, ab13, w24, u24, t20, t22 rx +_[0:9] the ixf1110 has a 100 ? differential termination on the chip and requires ac-coupling. 3 rd- y5, v4, ad15, ac16, ad14, ab14, v24, t24, u20, u22 rx -_[0:9] 4sd l1, r7, ab2, t4, u11, ac14, m20, aa16, y21, n24 mod_def[0:9] need to invert sd or force the ixf1110 to be permanently enabled by connecting mod_def[0:9] directly to ground. 5 vccr na na connect to filtered 3.3 v. 6 vcct na na connect to filtered 3.3 v. 7td- u5, u3, ad10, ac9, ad11, ab11, y22, w22, y20, v21 tx -_[0:9] the ixf1110 requires a 100 ? termination and for these lines to be ac-coupled. 8td+ t5, t3, ad9, ab9, ad12, ab12, y23, v22, y19, v20 tx +_[0:9] 9 veet na na connect to ground. n/a n/a l22, v17, ad18, r12, ab15, v12, y9, ac3, t2, p2 tx_disable[0:9] leave as no-connect. tx_fault tx_disable tx+ tx- rx+ rx- i 2 c_data i 2 c_clk mod_def rx_los 8 td+ 7 td- 2 rd+ 3 rd- 4 sd vccr 5 veer 1 vcct 6 veet 9 4.7 k ? ixf1110 serdes and gbic interfaces 1 x 9 module tx_fault_int rx_los_int mod_def_int vdd 3.3 v 4.7 k ? 4.7 k ?
intel ? ixf1110 10-port gigabit ethernet media access controller 76 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 n/a n/a m24, v23, y17, r15, w14, w11, w9, ac5, p8, l2 tx_fault[0:9] use external 4.7 k ? pull-down to ground to ensure proper operation. n/a n/a l22, v17, ad18, r12, ab15, v12, y9, ac3, t2, p2 rx_los_[0:9] use external 4.7 k ? pull-down to ground to ensure proper operation. n/a n/a g22, g23, j24, f22, e23, h24, g20, e22, g24, f24 i 2 c_data_[0:9] leave as no-connect. n/a n/a l19 i 2 c_clk leave as no-connect. n/a n/a b11 tx_fault_int leave as no-connect. n/a n/a b14 rx_los_int leave as no-connect. n/a n/a g15 mod_def_int leave as no-connect. table 20. 1 x 9-to-ixf1110 connection (continued) 1 x 9 pin # 1x9 pin name ixf1110 pin # 0:9 ixf1110 pin name description
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 77 document #: 250210 revision #: 004 rev. date: december 18, 2002 5.0 test specifications table 21 through table 34 on page 89 and figure 29 on page 80 through figure 38 on page 89 represent the target specifications of the following ixf1110 interfaces: ? cpu ? jtag ? transmit pause control ? gbic ? hardware reset ? led ? serdes ? spi4-2 ? i 2 c note: these specifications are not guar anteed and are subject to chan ge without notice. minimum and maximum values listed in table 23 through table 34 on page 89 apply over the recommended operating conditions specified in table 21 . table 21. absolute maximum ratings parameter symbol min max units supply voltage vdd -0.3 2.4 volts avdd -0.3 2.4 volts vdd2 -0.3 3.0 volts avdd2 -0.3 3.0 volts operating temperature ambient topa -15 +85 o c case topc ? +130 o c storage temperature tst -65 +150 o c caution: exceeding these values may cause perm anent damage. func tional operation under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
intel ? ixf1110 10-port gigabit ethernet media access controller 78 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 table 22. operating conditions parameter symbol min typ 1 max units recommended supply voltage vdd, avdd 1.71 1.80 1.89 volts vdd2, avdd2 2.375 2.50 2.625 volts operating current 1000base-sx idd and aidd ? 2.31 ? amps idd2 and aidd2 ? 0.310 ? amps recommended operating temperature ambient topa 0 ? 70 o c case with heat sink topc-hs 0 ? 119 o c case without heat sink topc-nhs 0 ? 118 o c power consumption 1000base-sx full- duplex tx and rx at 25 o c p?4.9?watts 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. table 23. 2.5 v lvttl and cmos i/o electrical characteristics parameter symbol min typ 1 max units test conditions input low voltage v il ? ? 0.70 v vcc = min input high voltage v ih 1.7 ? 3.3 v vcc = min output low voltage v ol ? ? 0.40 v vcc = min, iol = 3.9 ma output high voltage v oh 2.0 ? ? v vcc = min, ioh = -2.9 ma output leakage current i oz ??10 a vcc = max 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. 2. 3.3 v cmos tolerant. table 24. lvds i/o electrical characteristics parameter symbol min typ 1 max units test conditions input voltage range vi -0.20 ? vddmax+ 0.20 v? differential input voltage |vid| 100 ? ? mv @ 400 mhz input common-mode current icm??? a lvds input vos = 1.2 v threshold hysteresis th 25 ? ? mv ? differential input impedance r in 85 ? 115 ? typical 100 ? output low voltage v ol 0.95 ? ? v ? output high voltage v oh ?1.51v ? 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing.
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 79 document #: 250210 revision #: 004 rev. date: december 18, 2002 differential output voltage |vod| 330 ? 446 mv ? delta differential output voltage (complementary states) ? |vod| ? ? 25 mv ? offset (common- mode) voltage vos 1.12 ? 1.3 v ? output leakage current ioz ? ? 10 a? table 24. lvds i/o electrical characteristics (continued) parameter symbol min typ 1 max units test conditions 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing.
intel ? ixf1110 10-port gigabit ethernet media access controller 80 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 figure 29. cpu port read timing diagram figure 30. cpu port write timing diagram table 25. cpu timing parameters parameter symbol min typ 1 max units test conditions upx_add[12:0], upx_cs setup time t cas 10 ? ? ns ? upx_add[12:0], upx_cs hold time t cah 10 ? ? ns ? upx_rdy assertion to upx_rd de-assertion t crr 10 ? ? ns ? upx_rd high width t crh 24 (3x cycle) ??ns ? upx_data[31:0] to upx_rdy setup time t cdrs 10 ? ? ns ? 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. t cas t cah t crr t cdrs t cdrh t cdrd t crh upx_add[10:0] upx_rd upx_cs upx_data[31:0] upx_rdy t cas t cah t cwl t cdws t cdwd t cyd t cwh upx_add[10:0] upx_wr upx_cs upx_data[31:0] upx_rdy t cdwh
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 81 document #: 250210 revision #: 004 rev. date: december 18, 2002 upx_data[31:0] to upx_rd hold time t cdrh 8 ? 32 ns ? read upx_data[31:0] driving delay t cdrd 24 ? 120 ns ? upx_wr width t cwl 40 ? ? ns ? upx_rdy to upx_wr hold time t cwh 16 ? ? ns ? upx_data[31:0] to upx_wr setup time t cdws 10 ? ? ns ? upx_rdy to upx_data[31:0] hold time t cdwh 10 ? ? ns ? upx_data[31:0] latching delay t cdwd 8 ? 32 ns ? upx_rdy width in write cycle t cyd 24 ? 40 ns ? read upx_rdy de-assertion to upx_wr assertion t rtw 32 ? ? ns ? write upx_rdy de-assertion to upx_rd assertion t wtr 32 ? ? ns ? table 25. cpu timing parameters (continued) parameter symbol min typ 1 max units test conditions 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing.
intel ? ixf1110 10-port gigabit ethernet media access controller 82 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 figure 31. jtag timing diagram table 26. jtag timing parameters parameter symbol min typ 1 max units test conditions tclk cycle time t jc 90 ? ? ns ? tclk high time t jh 0.4 x t jc ? 0.6 x t jc ns ? tclk low time t jl 0.4 x t jc ? 0.6 x t jc ns ? tclk falling edge to tdo valid t jval ? ? 25 ns ? tms/tdi setup to tclk t jsu 20 ? ? ns ? tms/tdi hold from tclk t jsh 5??ns ? 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. tdo tms, tdi tclk tjval tjl tjh tjc tjsu tjsh
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 83 document #: 250210 revision #: 004 rev. date: december 18, 2002 figure 32. transmit pause control interface diagram table 27. transmit pause control interface parameters parameter symbol min typ 1 max units test conditions txpausefr width t pw 16 ? ? ns ? txpauseaddr[3:0] setup to txpausefr t su 16 ? ? ns ? txpauseaddr[3:0] hold from txpausefr t hd 32 ? ? ns ? txpausefr pulse to pulse t btp 48 ? ? ns ? 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. txpausefr txpauseaddr[3:0] tbtp tpw tsu thd
intel ? ixf1110 10-port gigabit ethernet media access controller 84 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 figure 33. gbic interrupt timing table 28. gbic interrupt timing parameters parameter symbol min typ 1 max units test conditions change of state on mod_def_9:0 or tx_fault_9:0 or rx_los_9:0 to assertion (active low) on mod_def_int or tx_fault_int or rx_los_int t di 24 ? ? ns ? 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. figure 34. hardware reset timing diagram table 29. hardware re set timing parameters parameter symbol min typ 1 max units test conditions reset pulse width t rw 100 ? ? ns ? reset recovery time t rt 4.11 ? ? s? 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. mod_def_9:0 tx_fault_9:0 rx_los_9:0 mod_def_int tx_fault_int rx_los_int tdi trw trt sys_res _______ cpu access
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 85 document #: 250210 revision #: 004 rev. date: december 18, 2002 figure 35. led timing diagram table 30. led ti ming parameters parameter symbol min typ 1 max units test conditions 2 led_clk cycle time t cyc 1.36 ? 1.40 ms ? led_clk high time t hi 680 ? 700 p s 50% duty cycle led_clk low time t low 680 ? 700 p s 50% duty cycle led_clk falling edge to led_data valid t datd 2 ? 5 ns ? led_clk rising edge to led_latch rising edge t lath 690 ? 700 p s ? led_clk falling edge to led_latch falling edge t latl 690 ? 700 p s ? 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. 2. flash rate = 100 ms, led mode 1. led_clk led_data led_latch tcyc tlow thi tdatd tlath tlatl
intel ? ixf1110 10-port gigabit ethernet media access controller 86 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 table 31 specifies the transmit elect rical specifications based on a recommended 1.8 v avdd termination voltage and the required 50 ? termination and table 32 specifies the receiver electrical specifications based on a recommended 1.8 v avdd termination voltage. figure 36 illustrates the timing requirements for the ixf1110 transmit and receive serdes signals. note: it is essential that both positive and negative driv e levels at the receiver input maintain a minimum voltage of 0.8 v relative to ground to help ensure proper circuit operation. figure 36. serdes timing diagram table 31. transmitter characteristics parameter symbol min typ 1 max units test conditions transmit differential signal level t v 600 770 1050 mvpp diff avdd terminated to 1.8 v; r load = 50 ? ; transmit eye width t t 800 ? ? ps ? differential signal rise/fall time ? 60 96 132 ps r load = 50 ? ; 20% to 80% max differential output impedance ? 60 100 150 ? diff dc transmitter short circuit current ? -100 ? 100 ma ? transmitter frequency ? 1.249875 1.25 1.250125 ghz reference oscillator 125 mhz +/- 100 ppm total transmitter output jitter ? 122 ps p-p total jitter at ber 1e-12 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. tt rt rv tv
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 87 document #: 250210 revision #: 004 rev. date: december 18, 2002 table 32. receiver characteristics parameter symbol min typ 1 max units test conditions receiver differential voltage requirement at center of receive-eye r v 200 ? ? mvp-p diff ? receive eye width r t 280 ? ? ps ? receiver termination impedance ? 40 ? 62.5 ? ? signal detect level ? 125 ? 400 mvp-p diff ? total receiver jitter tolerance ? ? ? 600 ps p-p total jitter at ber 1e-12 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing.
intel ? ixf1110 10-port gigabit ethernet media access controller 88 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 figure 37. spi4-2 transmit fifo status bus timing diagram table 33. spi4-2 transmit fifo status bus timing parameters parameter symbol min typ 1 max units test conditions tsclk falling edge to tstat[1:0] valid (active edge flipped to falling) t d 1 ? ? 280 ps ? tsclk rising edge to tstat[1:0] valid (default operation) t d 2 ? ? 280 ps ? 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. tsclk tstat[1:0] tstat[1:0] td2 td1
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 89 document #: 250210 revision #: 004 rev. date: december 18, 2002 figure 38. spi4-2 receive fifo status bus timing diagram table 34. spi4-2 receive fifo status bus timing parameters parameter symbol min typ 1 max units test conditions rstat[1:0] setup to rsclk rising edge (default operation) t su 12 ? ? ns ? rstat[1:0] hold from rsclk rising edge (default operation) t h 10.5 ? ? ns ? rstat[1:0] setup to rsclk falling edge (when active edge flipped to falling) t su 22 ? ? ns ? rstat[1:0] hold from rsclk falling edge (when active edge flipped to falling) t h 20.5 ? ? ns ? 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. rsclk rstat[1:0] rstat[1:0] tsu1 th1 th2 tsu2
intel ? ixf1110 10-port gigabit ethernet media access controller 90 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 figure 39. i 2 c bus timing diagram figure 40. i 2 c write cycle diagram table 35. i 2 c ac timing characteristics parameter symbol min typ 1 max units test conditions clock frequency, scl f scl ? ? 100 khz ? clock pulse width low t low 4.7 ? s? clock pulse width high t high 4.0 ? s? noise suppression t i ? ? 100 ns ? clock low to data valid out t aa 0.1 ? 4.5 s? time bus must be free before a new transmission starts t buf 4.7 ? ? s? start hold time t hd.sta 4.0 ? ? s? start setup time t su.sta 4.7 ? ? s? data in hold time t hd.dat 0? ? s? data in setup time t su.dat 200 ? ? ns ? inputs rise time t r ??1.0 s? inputs fall time t f ? ? 300 ns ? 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. i 2 c_clk i 2 c_data out t dh t hd.sta t aa t buf t su.sta t high t r t su.sto t su.dat t hd.dat t low t f i 2 c_data in t low ack 8th bit word n i 2 c_clk i 2 c_data stop condition start condition t wr (1)
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 91 document #: 250210 revision #: 004 rev. date: december 18, 2002 stop setup time t su.sto 4.7 ? ? s? data out hold time t dh 100 ? ? ns ? write cycle time t wr ??10ms ? table 35. i 2 c ac timing characteristics (continued) parameter symbol min typ 1 max units test conditions 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing.
intel ? ixf1110 10-port gigabit ethernet media access controller 92 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 6.0 register definitions 6.1 introduction this section provides information on the location and functionality of the control and status registers contained in the intel ? ixf1110. 6.2 document structure this document is structured to give a general overview of the register map and an in-depth description of each bit of a register in later sections. 6.3 graphical representation figure 41 represents an overview of the ixf1110 global control status regist ers that are used to configure or report on all ports.
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 93 document #: 250210 revision #: 004 rev. date: december 18, 2002 figure 41. memory overview diagram global configuration -rx block configuration -tx block configuraiton port 9 mac control & statistics port 8 mac control & statistics port 7 mac control & statistics port 6 mac control & statistics port 5 mac control & statistics port 0 mac control & statistics port 1 mac control & statistics port2 mac control & statistics port 3 mac control & statistics port 4 mac control & statistics 0x7ff 0x000 0x180 0x100 0x080 0x200 0x280 0x300 0x380 0x400 0x480 0x500
intel ? ixf1110 10-port gigabit ethernet media access controller 94 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 6.4 per port registers the following section covers all of the registers that are repli cated in each of th e 10 ports in the ixf1110. these registers perform an identical function in each port. the address vector for the ixf1110 is 11 bits wi de. this allows for 7 bits of port-specific access and a 4-bit vector to address each port and all gl obal registers. the address format is shown in figure 42 . figure 42. register overview diagram port select & global registers per-port registers 10 0 6
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 95 document #: 250210 revision #: 004 rev. date: december 18, 2002 6.5 memory map table 36 through table 44 on page 101 provide the ixf1110 memory maps. a number of global control and status registers are used to configur e or report on all ports, and some registers are replicated on a per-port basis. note: all registers in the ixf1110 are 32 bits. table 36. mac control register map register bit size mode 1 ref page offset mac control registers (port index + offset) station address low 32 r/w 102 0x00 station address high 32 r/w 102 0x01 reserved 32 ro ? 0x02 fdfc type 32 r/w 102 0x03 reserved 32 ro ? 0x04 reserved 32 ro ? 0x05 reserved 32 ro ? 0x06 fc tx timer value 32 r/w 102 0x07 fdfc address low 32 r/w 103 0x08 fdfc address high 32 r/w 103 0x09 reserved 32 ro ? 0x0a reserved 32 ro ? ox0b ipg transmit time 32 r/w 103 0x0c reserved 32 r/w -- 0x0d pause threshold 32 r/w 103 0x0e max frame size 32 r/w 104 0x0f reserved 32 ro ? 0x10 reserved 32 ro ? 0x11 fc enable 32 r/w 104 0x12 reserved 32 ro ? 0x13 short runts threshold 32 r/w 104 0x14 discard unknown control frame 32 r/w 104 0x15 rx config word 32 r/w 105 0x16 tx config word 32 r/w 106 0x17 diverse config 32 r/w 106 0x18 rx packet filter control 32 r/w 107 0x19 port multicast address low 32 r/w 109 0x1a port multicast address high 32 r/w 109 0x1b 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 96 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 table 37. mac rx statistics register map register bit size mode 1 ref page offset mac rx statistics registers (port index + offset) rxoctetstotalok 32 rr 110 0x20 rxoctetsbad 32 rr 110 0x21 rxucpckts 32 rr 110 0x22 rxmcpkts 32 rr 110 0x23 rxbcpkts 32 rr 110 0x24 rxpkts64octets 32 rr 110 0x25 rxpkts65to127octets 32 rr 110 0x26 rxpkts128to255octets 32 rr 110 0x27 rxpkts256to511octets 32 rr 110 0x28 rxpkts512to1023octets 32 rr 110 0x29 rxpkts1024to1518octets 32 rr 110 0x2a rxpkts1519tomaxoctets 32 rr 110 0x2b rxfcserrors 32 rr 110 0x2c rxtagged 32 rr 110 0x2d rxdataerror 32 rr 110 0x2e rxalignerrors 32 rr 110 0x2f rxlongerrors 32 rr 110 0x30 rxjabbererrors 32 rr 110 0x31 rxpausemaccontrolcounter 32 rr 110 0x32 rxunknownmaccontrolframecounter 32 rr 110 0x33 rxverylongerrors 32 rr 110 0x34 rxrunterrors 32 rr 110 0x35 rxshorterrors 32 rr 110 0x36 rxcarrierextenderror 32 rr 110 0x37 rxsequenceerrors 32 rr 110 0x38 rxsymbolerrors 32 rr 110 0x39 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 97 document #: 250210 revision #: 004 rev. date: december 18, 2002 table 38. mac tx statistics register map register bit size mode 1 ref page offset max tx statistics registers (port index + offset) txoctetstotalok 32 rr 114 0x40 txoctetsbad 32 rr 114 0x41 txucpkts 32 rr 114 0x42 txmcpkts 32 rr 114 0x43 txbcpkts 32 rr 114 0x44 txpkts64octets 32 rr 114 0x45 txpkts65to127octets 32 rr 114 0x46 txpkts128to255octets 32 rr 114 0x47 txpkts256to511octets 32 rr 114 0x48 txpkts512to1023octets 32 rr 114 0x49 txpkts1024to1518octets 32 rr 114 0x4a txpkts1519tomaxoctets 32 rr 114 0x4b txdeferred 32 rr 114 0x4c txtotalcollisions 32 rr 114 0x4d txsinglecollisions 32 rr 114 0x4e txmultiplecollisions 32 rr 114 0x4f txlatecollisions 32 rr 114 0x50 txexcessivecollisionerrors 32 rr 114 0x51 txexcessivedeferralerrors 32 rr 114 0x52 txexcessivelengthdrop 32 rr 114 0x53 txunderrun 32 rr 114 0x54 txtagged 32 rr 114 0x55 txcrcerror 32 rr 114 0x56 txpauseframes 32 rr 114 0x57 txflowcontrolcollisionssend 32 rr 114 0x58 1. ro = read only; rr = clear on read; w = write; r/w = read/write table 39. global status and configuration register map register bit size mode 1 ref page address port enable 32 r/w 118 0x500 reserved 32 ro ? 0x501 link led enable 32 r/w 119 0x502 reserved 32 ro ? 0x503 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 98 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 reserved 32 ro ? 0x504 reserved 32 ro ? 0x505 reserved 32 ro ? 0x506 reserved 32 ro ? 0x507 cpu interface 32 r/w 120 0x508 led control 32 r/w 120 0x509 led flash rate 32 r/w 120 0x50a led fault disable 32 r/w 121 0x50b jtag id 32 r/w 122 0x50c table 40. rx block register map register bit size mode 1 ref page address rx fifo high watermark port 0 32 r/w 123 0x580 rx fifo high watermark port 1 32 r/w 123 0x581 rx fifo high watermark port 2 32 r/w 123 0x582 rx fifo high watermark port 3 32 r/w 123 0x583 rx fifo high watermark port 4 32 r/w 123 0x584 rx fifo high watermark port 5 32 r/w 123 0x585 rx fifo high watermark port 6 32 r/w 123 0x586 rx fifo high watermark port 7 32 r/w 123 0x587 rx fifo high watermark port 8 32 r/w 123 0x588 rx fifo high watermark port 9 32 r/w 123 0x589 rx fifo low watermark port 0 32 r/w 124 0x58a rx fifo low watermark port 1 32 r/w 124 0x58b rx fifo low watermark port 2 32 r/w 124 0x58c rx fifo low watermark port 3 32 r/w 124 0x58d rx fifo low watermark port 4 32 r/w 124 0x58e rx fifo low watermark port 5 32 r/w 124 0x58f rx fifo low watermark port 6 32 r/w 124 0x590 rx fifo low watermark port 7 32 r/w 124 0x591 rx fifo low watermark port 8 32 r/w 124 0x592 rx fifo low watermark port 9 32 r/w 124 0x593 rx fifo number of frames removed on port 0 32 rr 126 0x594 rx fifo number of frames removed on port 1 32 rr 126 0x595 1. ro = read only; rr = clear on read; w = write; r/w = read/write table 39. global status and configuration register map (continued) register bit size mode 1 ref page address 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 99 document #: 250210 revision #: 004 rev. date: december 18, 2002 rx fifo number of frames removed on port 2 32 rr 126 0x596 rx fifo number of frames removed on port 3 32 rr 126 0x597 rx fifo number of frames removed on port 4 32 rr 126 0x598 rx fifo number of frames removed on port 5 32 rr 126 0x599 rx fifo number of frames removed on port 6 32 rr 126 0x59a rxfifo number of frames removed on port 7 32 rr 126 0x59b rx fifo number of frames removed on port 8 32 rr 126 0x59c rx fifo number of frames removed on port 9 32 rr 126 0x59d reserved 32 ro ? 0x59e rx fifo errored frames drop enable 32 r/w 128 0x59f rx fifo overflow event 32 rr 129 0x5a0 table 41. tx block register map register bit size mode 1 ref page address tx fifo high watermark port 0 32 r/w 131 0x600 tx fifo high watermark port 1 32 r/w 131 0x601 tx fifo high watermark port 2 32 r/w 131 0x602 tx fifo high watermark port 3 32 r/w 131 0x603 tx fifo high watermark port 4 32 r/w 131 0x604 tx fifo high watermark port 5 32 r/w 131 0x605 tx fifo high watermark port 6 32 r/w 131 0x606 tx fifo high watermark port 7 32 r/w 131 0x607 tx fifo high watermark port 8 32 r/w 131 0x608 tx fifo high watermark port 9 32 r/w 131 0x609 tx fifo low watermark port 0 32 r/w 131 0x60a tx fifo low watermark port 1 32 r/w 132 0x60b tx fifo low watermark port 2 32 r/w 132 0x60c tx fifo low watermark port 3 32 r/w 132 0x60d tx fifo low watermark port 4 32 r/w 132 0x60e tx fifo low watermark port 5 32 r/w 132 0x60f tx fifo low watermark port 6 32 r/w 132 0x610 tx fifo low watermark port 7 32 r/w 132 0x611 tx fifo low watermark port 8 32 r/w 132 0x612 tx fifo low watermark port 9 32 r/w 132 0x613 1. ro = read only; rr = clear on read; w = write; r/w = read/write table 40. rx block register map (continued) register bit size mode 1 ref page address 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 100 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 tx fifo mac transfer threshold port 0 32 r/w 134 0x614 tx fifo mac transfer threshold port 1 32 r/w 134 0x615 tx fifo mac transfer threshold port 2 32 r/w 134 0x616 tx fifo mac transfer threshold port 3 32 r/w 134 0x617 tx fifo mac transfer threshold port 4 32 r/w 134 0x618 tx fifo mac transfer threshold port 5 32 r/w 134 0x619 tx fifo mac transfer threshold port 6 32 r/w 134 0x61a tx fifo mac transfer threshold port 7 32 r/w 134 0x61b tx fifo mac transfer threshold port 8 32 r/w 134 0x61c tx fifo mac transfer threshold port 9 32 r/w 134 0x61d tx fifo overflow event 32 rr 137 0x61e reserved 32 ro ? 0x61f reserved 32 ro ? 0x620 tx fifo info out of sequence 32 rr 138 0x621 tx fifo number of frames removed on port 0 32 rr 139 0x622 tx fifo number of frames removed on port 1 32 rr 139 0x623 tx fifo number of frames removed on port 2 32 rr 139 0x624 tx fifo number of frames removed on port 3 32 rr 139 0x625 tx fifo number of frames removed on port 4 32 rr 139 0x626 tx fifo number of frames removed on port 5 32 rr 139 0x627 tx fifo number of frames removed on port 6 32 rr 139 0x628 tx fifo number of frames removed on port 7 32 rr 139 0x629 tx fifo number of frames removed on port 8 32 rr 139 0x62a tx fifo number of frames removed on port 9 32 rr 139 0x62b table 42. spi4-2 block register map register bit size mode 1 ref page address spi4-2 rx burst size 32 r/w 140 0x700 spi4-2 rx training 32 r/w 140 0x701 spi4-2 calendar 32 r/w 141 0x702 spi4-2 tx synchronization 32 r/w 142 0x703 1. ro = read only; rr = clear on read; w = write; r/w = read/write table 41. tx block register map (continued) register bit size mode 1 ref page address 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 101 document #: 250210 revision #: 004 rev. date: december 18, 2002 table 43. serdes block register map register bit size mode 1 ref page address tx and rx ac/dc coupling selection 32 r/w 142 0x780 reserved 32 ro ? 0x781 reserved 32 ro ? 0x782 reserved 32 ro ? 0x783 reserved 32 ro ? 0x784 reserved 32 ro ? 0x785 reserved 32 ro ? 0x786 tx and rx power-down ports 0-9 32 r/w 143 0x787 reserved 32 ro ? 0x788 reserved 32 ro ? 0x789 reserved 32 ro ? 0x78a reserved 32 ro ? 0x78b reserved 32 ro ? 0x78c reserved 32 ro ? 0x78d reserved 32 ro ? 0x78e reserved 32 ro ? 0x78f reserved 32 ro ? 0x790 reserved 32 ro ? 0x791 reserved 32 ro ? 0x792 rx signal detect level ports 0-9 32 ro 143 0x793 reserved 32 ro ? 0x794 reserved 32 ro ? 0x795 reserved 32 ro ? 0x796 reserved 32 ro ? 0x797 reserved 32 ro ? 0x798 1. ro = read only; rr = clear on read; w = write; r/w = read/write table 44. gbic block register map register bit size mode 1 ref page address gbic status register ports 0-9 32 ro 144 0x799 gbic control register ports 0-9 32 r/w 144 0x79a i 2 c control register ports 0-9 32 r/w 146 0x79b i 2 c data register ports 0-9 32 r/w 146 0x79c 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 102 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 6.5.1 mac control registers table 45 through table 62 on page 109 provide details on the control an d status registers associated with each mac port. the register address is ? port_index + 0x** ?, where the port index is set at any value from 0x000 through 0x500. all registers are 32 bits. table 45. station address register low (addr: port_index + 0x00) bit name description type 1 default 31:0 station address low source mac address bits 31-0. this address is inserted in the source address field when transmitting pause frames, and is also used to compare against unicast pause frames at the receiving side. r/w 0x00000000 1. ro = read only; rr = clear on read; w = write; r/w = read/write table 46. station address register high (addr: port_index + 0x01) bit name description type 1 default 31:16 reserved reserved ro 0x0000 15:0 station address high source mac address bits 47-32. this address is inserted in the source address field when transmitting pause frames, and is also used to compare against unicast pause frames at the receiving side. r/w 1. ro = read only; rr = clear on read; w = write; r/w = read/write table 47. fdfc type register (addr: port_index + 0x03) bit name description type 1 default 31:16 reserved reserved ro 0x0000 15:0 fdfc type contains the value of the type field transmitted in an internally generated flow control (pause) frame. internally generated flow control frames are generated via the external pause interface or when the rx fifo exceeds its high watermark. r/w 0x8808 1. ro = read only; rr = clear on read; w = write; r/w = read/write table 48. fc tx timer value register (addr: port_index + 0x07) bit name description type 1 default 31:16 reserved reserved ro 0x0000 15:0 fc tx timer value the pause length sent to the receiving station in 512 bit times r/w 0x005e 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 103 document #: 250210 revision #: 004 rev. date: december 18, 2002 table 49. fdfc address low register (addr: port_index + 0x08) bit name description type 1 default 31:0 fdfc address low contains the value of the lowest 32 bits of the destination address field transmitted in an internally generated flow control (pause) frame. internally generated flow control frames are generated via the external pause interface or when the rx fifo exceeds it high watermark. r/w 0xc2000001 1. ro = read only; rr = clear on read; w = write; r/w = read/write table 50. fdfc address high register (addr: port_index + 0x09) bit name description type 1 default 31:16 reserved reserved ro 0x0000 15:0 fdfc address high contains the value of the highest 16 bits of the destination address filed transmitted in an internally generated flow control (pause) frame. internally generated flow control frames are generated via the external pause interface or when the rx fifo exceeds it high watermark. r/w 0x0180 1. ro = read only; rr = clear on read; w = write; r/w = read/write table 51. ipg transmit time register (addr: port_index + 0x0c) bit name description type 1 default 31:10 reserved reserved ro 0x0000 9:0 ipg transmit time ipg time for back-to-back transmissions (specified in multiples of 512 bit times) note: the value specified in this register should be four less than desired. r/w 0x0008 1. ro = read only; rr = clear on read; w = write; r/w = read/write table 52. pause threshold register (addr: port_index + 0x0e) bit name description type 1 default 31:16 reserved reserved ro 0x0000 15:0 pause threshold when a pause frame is sent, an internal timer checks when a new pause frame must be scheduled for transmission to keep the link partner in pause mode. the pause threshold value is the minimum time to send before the earlier pause frame is aged out (specified in multiples of 512 bit times). r/w 0x002f 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 104 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 table 53. max frame size register (addr: port_index + 0x0f) bit name description type 1 default 31:14 reserved reserved ro 0x0000 13:0 max frame size the maximum frame size the mac can receive or transmit without activating any error counters, and without truncation. the maximum frame size is internally adjusted by +4 if vlan is tagged. r/w 0x05ee 1. ro = read only; rr = clear on read; w = write; r/w = read/write table 54. fc enable register (addr: port_index + 0x12) bit name description type 1 default register description: indicates flow control settings of the ixf1110. 0x00000007 31:2 reserved reserved ro 0x00000001 1tx fd fc 1 = enable tx fd flow control 0 = disables r/w 1 0 rx fd fc 1 = enable rx fd flow control 0 = disables r/w 1 1. ro = read only; rr = clear on read; w = write; r/w = read/write table 55. short runts threshold register (addr: port_index + 0x14) bit name description type 1 default 31:5 reserved reserved ro 0x0000000 4:0 short runts threshold holds the value in bytes, which applies to the threshold in determining between runts and short. r/w 01000 1. ro = read only; rr = clear on read; w = write; r/w = read/write table 56. discard unknown control frame register (addr: port_index + 0x15) bit name description type 1 default 31:1 reserved reserved ro 0x00000000 0 discard unknown control frame 0 = keep unknown control frames 1 = discard unknown control frames. r/w 0 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 105 document #: 250210 revision #: 004 rev. date: december 18, 2002 table 57. rx config word register (addr: port_index + 0x16) bit name description type 1 default register description: this register is used in the ixf1110 only for auto-negotiation. the contents of this register are the ?config_reg? rece ived from the link partner, as described in ieee 802.3, subclause 37.2.1. 0x00000000 31:22 reserved reserved ro 0 21 an_complete auto-negotiation complete. this bit remains cleared from the time auto-negotiation is reset until auto- negotiation reaches the ?link_ok? state. it remains set until auto-negotiation is disabled or restarted. (this bit is only valid if auto-negotiation is enabled.) ro 0 20 rx sync 0 = 1 = loss of synchronization bit synchronization (bit remains low until register is read) rr 0 19 rx config 0 = 1 = receiving idle/data stream receiving /c/ ordered sets ro 18 config changed 0 = 1 = rxconfigword has changed since last read rxconfigword has not changed since last read (this bit remains high until register is read) rr 0 17 invalid word 0 = 1 = have not received an invalid symbol have received an invalid symbol (this bit remains high until register is read) rr 0 16 carrier sense 0 = 1 = device is not receiving idle characters (carrier sense is true). device is receiving idle characters (carrier sense is false). ro 0 15 next page next page request ro 0 14 reserved reserved ro 0 13:12 remotefault[1:0] remote fault definitions: 00 = no error, link okay 01 = offline 10 = link failure 11 = auto-negotiation_error ro 00 11:9 reserved reserved ro 000 8 asym pause asym pause (ability to send pause frames) ro 0 7 sym pause syn pause (ability to send and receive pause frames) ro 0 6 half duplex half-duplex ro 0 5 full duplex full-duplex ro 0 4:0 reserved reserved ro 00000 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 106 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 table 58. tx config word register (addr: port_index + 0x17) bit name description type 1 default register description: this register is used in the ixf1110 for auto-negotiation only. the contents of this register are sent as the config_word. 0x000001a0 31:16 reserved reserved ro 0x0000 15 nextpage next page request r/w 0 14 reserved reserved ro 0 13:12 2 remote fault [1:0] remote fault definitions: 00 = no error, link okay 01 = offline 10 = link failure 11 = auto-negotiation_error r/w 00 11:9 reserved reserved ro 000 8 asym pause ability to send pause frames r/w 1 7 sym pause ability to send and receive pause frames r/w 1 6 half duplex half-duplex r/w 0 5 full duplex full-duplex r/w 1 4:0 reserved reserved ro 00000 1. ro = read only; rr = clear on read; w = write; r/w = read/write 2. there is no way to automatically update the state of the remote fault bits for transmission. the state of these bits must be set by the system controller vi a the up interface prior to enabling auto-negotiation. table 59. diverse config register (addr: port_index + 0x18) bit name description type 1 default register description: this register contains various configuration bits for general use. 0x0000110d 31:16 reserved reserved ro 0x0000 31:17 reserved reserved ro 0x0000 16:9 reserved reserved ro 000100 8 reserved reserved ro 1 7 pad_enable enable padding of undersized packets r/w 0 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 107 document #: 250210 revision #: 004 rev. date: december 18, 2002 6 crc_add enable automatic crc appending r/w 0 5 an_enable auto-negotiation enable: 1 = setting this bit to 1 puts the port in an auto-neogatiate mode and starts auto- negoation. 0 = setting this bit to 0 disables auto- negotiation and puts the ixf1110 in forced mode. note: since default = 0, this bit must be changed to a 1 via the cpu to enable auto- negotiation. auto-negotiation can be restarted by de-asserting this bit, then re- aserting. r/w 0 4:0 reserved reserved ro 01101 table 60. rx packet filter control register (addr: port_index + 0x19) bit name description type 1 default register description: this register allows for specific packet types to be marked for filtering, and is used in conjunction with the rx fifo errored frames drop enable register 0x00000000 31:6 reserved reserved ro 0x000000 5 crc error pass 2 this bit enables a global filter on frames with a crc error. when crcerrorpass = 0, all frames with a crc error are marked as bad. note: when used in conjunction with the rx fifo erroredframedropenable[9:0] register (see table 75 on page 128 ). this allows the frame to be dropped in the rx fifo. otherwise, the frame is sent across the spi4-2 interface but marked as an eop abort frame. when crcerrorpass = 1, frames with a crc error are not marked as bad and are passed to the spi4-2 interface for transfer as good frames, regardless of the state of the framedropen[9:0] bits. r/w 0 1. ro = read only; rr = clear on read; w = write; r/w = read/write 2. jumbo frames (1519 - 9600 bytes), matching the filter conditions, which would cause the frame to be dropped by the rx fifo, will not be dropped. instead, ju mbo frames that are marked to be dropped by the rx fifo, based on the filter setting in this register, will still be sent across the spi4-2 interface, but will be marked as an eop abort frame. thus, jumbo frames matc hing the filter conditions will not be counted in the rx fifo number of frames removed register bec ause they are not removed by the rx fifo. only standard packet sizes (64 - 1518 bytes) meeting the filter conditions set in this register will actually be dropped by the rx fifo and counted in the rx fifo number of frames removed. 3. frames are dropped only when the appropriate bits are set in the rx fifo errored frame drop enable register ( table 75 on page 128 ). when the appropriate bits are not set, the frames are sent across the spi4-2 interface and marked as eop abort frames. table 59. diverse config register (addr: port_index + 0x18) (continued) bit name description type 1 default 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 108 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 4 pause frame pass 2 this bit enables a global filter on pause frames. when pauseframepass = 0, all pause frames are marked as bad. note: when used in conjunction with the rx fifo erroredframedropenable[9:0] register (see table 75 on page 128 ). this allows the frame to be dropped in the rx fifo. otherwise, the frame is sent across the spi4-2 interface but marked as an eop abort frame. when pauseframepass = 1, all pause frames are not marked as bad and are passed to the spi4-2 interface for transfer as good frames, regardless of the state of the framedropen[9:0] bits. r/w 0 3 vlan drop en 2 this bit enables a global filter on vlan frames. when vlandropen = 0, all vlan frames are passed to the spi4-2 interface. when vlandropen = 1, all vlan frames are dropped. 3 r/w 0 2 b/cast drop en 2 this bit enables a global filter on broadcast frames. when b/castdropen = 0, all broadcast frames are passed to the spi4-2 interface. when b/castdropen = 1, all broadcast frames are dropped. 3 r/w 0 1 m/cast match en 2 this bit enables a filter on multicast frames. if this bit = 0, all multicast frames are good and are passed to the spi4-2 interface. if this bit = 1, only multicast frames with a destination address that matches the portmulticastaddress is forwarded. all other multicast frames are dropped. 3 r/w 0 0 u/cast match en 2 this bit enables a filter on unicast frames. if this bit = 0, all unicast frames are good and are passed to the spi4-2 interface. if this bit = 1, only unicast frames with a destination address that matches the station address is forwarded. all other unicast frames are dropped. 3 r/w 0 table 60. rx packet filter control regi ster (addr: port_index + 0x19) (continued) bit name description type 1 default 1. ro = read only; rr = clear on read; w = write; r/w = read/write 2. jumbo frames (1519 - 9600 bytes), matching the filt er conditions, which would cause the frame to be dropped by the rx fifo, will not be dropped. instead, jumbo frames that are marked to be dropped by the rx fifo, based on the filter setting in this register, will still be sent across the spi4-2 interface, but will be marked as an eop abort frame. thus, jumbo frames matc hing the filter conditions will not be counted in the rx fifo number of frames removed register bec ause they are not removed by the rx fifo. only standard packet sizes (64 - 1518 bytes) meeting the filter conditions set in this register will actually be dropped by the rx fifo and counted in the rx fifo number of frames removed. 3. frames are dropped only when the appropriate bits are set in the rx fifo errored frame drop enable register ( table 75 on page 128 ). when the appropriate bits are not set, the frames are sent across the spi4-2 interface and marked as eop abort frames.
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 109 document #: 250210 revision #: 004 rev. date: december 18, 2002 table 61. port multicast address low register (addr: port_index + 0x1a) bit name description type 1 default 31:0 port multicast address low this address is used to compare against multicast frames at the receiving side if multicast filtering is enabled. this register contains bits 31:0 of the address. r/w 0x00000000 1. ro = read only; rr = clear on read; w = write; r/w = read/write table 62. port multicast address high register (addr: port_index + 0x1b) bit name description type 1 default 31:16 reserved reserved ro 0x0000 15:0 port multicast address high this address is used to compare against multicast frames at the receiving side if multicast filtering is enabled. this register contains bits 47:32 of the address. r/w 0x0000 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 110 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 6.5.2 mac rx statisti cs register overview the mac rx statistics registers contain the mac receiver statistic counters and are cleared when read. the software polls these registers and accumu lates values to ensure that the counters do not wrap. the 32-bit counters wrap after approximat ely 30 seconds. table 63 covers the mac rx statistics registers for all 10 mac ports. the address is identical to the port number. table 63. mac rx statistics registers (addr: port_index + 0x20 - port_index + 0x39) name description address type 1 default rxoctetstotalok counts the bytes received in all legal frames, including all bytes from the destination mac address to and including the crc. the initial preamble and sfd bytes are not counted. port_index + 0x20 rr 0x00000000 rxoctetsbad 2 counts the bytes received in all bad frames of a size greater than or equal to 64 bytes. a bad frame is defined as a properly framed packet containing a crc, alignment error, or code violation. the 64-byte value is measured from the destination address, up to and including crc. the initial preamble and sfd are not included in this value. note: this register does not increment the bad octet count on undersized receive packets. port_index + 0x21 rr 0x00000000 rxucpkts the total number of unicast packets received (excluding bad packets) note: this count includes non-pause control and vlan packets, which are also counted in other counters. these packet types are counted twice. take care when summing register counts for reporting mib information. port_index + 0x22 rr 0x00000000 rxmcpkts the total number of multicast packets received (excluding bad packets) note: this count includes pause control packets, which are also counted in the pausemaccontrol- receivedcounter. these packet types are counted twice. take care when summing register counts for reporting mib information. port_index + 0x23 rr 0x00000000 rxbcpkts the total number of broadcast packets received (excluding bad packets) port_index + 0x24 rr 0x00000000 rxpkts64octets the total number of packets received (including bad packets) that were 64 octets in length. incremented for tagged packets with a length of 64 bytes, including tag field port_index + 0x25 rr 0x00000000 1. ro = read only; rr = clear on read; w = write; r/w = read/write 2. when sending in large frames, the counters can on ly deal with certain limits. the behavior of the longerrors and verylongerrors counters is as follow s: verylongerrors counts frames that are 2*maxframesize, dependent on where the maxframesize variable is set. if maxframesize sets greater than half of the available count in rxoctetsbad (2 ^14-1), verylongerrors is never incremented, but longerrors is incremented. this is due to a limitation in the counter size, which means that an accurate count will not occur in the rxoctetsbad counter if the frame is larger than 2^14-1. maxframesize is determined by the settings in the ?max frame size register (addr: port_index + 0x0f)? on page 104 .
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 111 document #: 250210 revision #: 004 rev. date: december 18, 2002 rxpkts65to127 octets the total number of packets received (including bad packets) that were [65-127] octets in length. incremented for tagged packets with a length of 65 - 127 bytes, including tag field port_index + 0x26 rr 0x00000000 rxpkts128to255 octets the total number of packets received (including bad packets) that were [128-255] octets in length. incremented for tagged packets with a length of 128-255 bytes, including tag field port_index + 0x27 rr 0x00000000 rxpkts256to511 octets the total number of packets received (including bad packets) that were [256-511] octets in length. incremented for tagged packets with a length of 256 - 511 bytes, including tag field port_index + 0x28 rr 0x00000000 rxpkts512to1023 octets the total number of packets received (including bad packets) that were [512-1023] octets in length. incremented for tagged packets with a length of 512 - 1023 bytes, including tag field port_index + 0x29 rr 0x00000000 rxpkts1024to1518 octets the total number of packets received (including bad packets) that were [1024-1518] octets in length. incremented for tagged packet with a length between 1024-1522, including the tag port_index + 0x2a rr 0x00000000 rxpkts1519tomax octets the total number of packets received (including bad packets) that were >1518 octets in length. incremented for tagged packet with a length between 1523-max frame size, including the tag port_index + 0x2b rr 0x00000000 rxfcserrors number of frames received with legal size, but with wrong crc field (also called fcs field) note: legal size is 64 bytes through the value stored in the ?max frame size register (addr: port_index + 0x0f)? on page 104 . port_index + 0x2c rr 0x00000000 rxtagged number of frames (including bad packets) with vlan tag (type field = 0x8100) port_index + 0x2d rr 0x00000000 rxdataerror number of frames received with legal length, containing a code violation (signaled with rx_err on rgmii) note: the ixf1110 does not support an rgmii interface; thus, this counter is not applicable to the ixf1110. port_index + 0x2e rr 0x00000000 rxalignerrors frames with a legal frame size, but containing less than 8 additional bits. the crc of the frame is wrong when the additional bits are stripped. if the crc is ok, the frame is not counted, but treated as an ok frame. port_index + 0x2f rr 0x00000000 table 63. mac rx statistics registers (addr: port_index + 0x20 - port_index + 0x39) name description address type 1 default 1. ro = read only; rr = clear on read; w = write; r/w = read/write 2. when sending in large frames, the counters can only deal with certain limits. the behavior of the longerrors and verylongerrors counters is as fo llows: verylongerrors counts frames that are 2*maxframesize, dependent on where the maxframesize variable is set. if maxframesize sets greater than half of the available count in rxoctetsbad (2^14-1), verylongerrors is never incremented, but longerrors is incremented. this is due to a limitation in the counter size, which means that an accurate count will not occur in the rxoctetsbad counter if the frame is larger than 2^14-1. maxframesize is determined by the settings in the ?max frame size register (addr: port_index + 0x0f)? on page 104 .
intel ? ixf1110 10-port gigabit ethernet media access controller 112 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 rxlongerrors 2 frames bigger than the maximum allowed, with both ok crc and the integral number of octets default maximum allowed is 1518 bytes untagged and 1522 bytes tagged, but the value can be changed by a register frames bigger than the larger of 2*maxframesize and 50000 bits are not counted here, but counted in the verylongerror counter. port_index + 0x30 rr 0x00000000 rxjabbererrors frames bigger than the maximum allowed, with either a bad crc or a non-integral number of octets. the default maximum allowed is 1518 bytes untagged and 1522 bytes tagged, but the value can be changed by a register. frames bigger than the larger of 2*maxframesize and 50000 bits are not counted here, but counted in the verylongerror counter. port_index + 0x31 rr 0x00000000 rxpausemac controlcounter number of pause mac control frames received port_index + 0x32 rr 0x00000000 rxunknownmac controlframe counter number of mac control frames received with an op code different from 0001 (pause) port_index + 0x33 rr 0x00000000 rxverylongerrors 2 frames bigger than the larger of 2*maxframesize and 50000 bits port_index + 0x34 rr 0x00000000 rxrunterrors the total number of packets received that are less than 64 octets in length, but longer than or equal to 96 bit times. note: rxrunterrors is not supported in the ixf1110. any runt or short packets received are not counted in this register. note: the ?shortruntsthreshold? register controls the byte count used to determine the difference between runts and shorts, and therefore controls which counter is incremented for a given frame size. this counter is only updated after receipt of two good frames. port_index + 0x35 rr 0x00000000 rxshorterrors the total number of packets received that are less than 96 bit times, which corresponds to a 4- byte frame with a well formed preamble and sfd. this counter indicates fragment sizes illegal in all modes, and is only fully updated after reception of a good frame following a fragment. note: rxshorterrors is not supported in the ixf1110. any runt or short packets received are not counted in this register. port_index + 0x36 rr 0x00000000 table 63. mac rx statistics registers (addr: port_index + 0x20 - port_index + 0x39) name description address type 1 default 1. ro = read only; rr = clear on read; w = write; r/w = read/write 2. when sending in large frames, the counters can on ly deal with certain limits. the behavior of the longerrors and verylongerrors counters is as follow s: verylongerrors counts frames that are 2*maxframesize, dependent on where the maxframesize variable is set. if maxframesize sets greater than half of the available count in rxoctetsbad (2 ^14-1), verylongerrors is never incremented, but longerrors is incremented. this is due to a limitation in the counter size, which means that an accurate count will not occur in the rxoctetsbad counter if the frame is larger than 2^14-1. maxframesize is determined by the settings in the ?max frame size register (addr: port_index + 0x0f)? on page 104 .
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 113 document #: 250210 revision #: 004 rev. date: december 18, 2002 rxcarrierextend error gigabit half-duplex event only note: n/a - half-duplex only port_index + 0x37 rr 0x00000000 rxsequenceerrors records the number of sequencing errors that occur. port_index + 0x38 rr 0x00000000 rxsymbolerrors records the number of symbol errors encountered. port_index + 0x39 rr 0x00000000 table 63. mac rx statistics registers (addr: port_index + 0x20 - port_index + 0x39) name description address type 1 default 1. ro = read only; rr = clear on read; w = write; r/w = read/write 2. when sending in large frames, the counters can only deal with certain limits. the behavior of the longerrors and verylongerrors counters is as fo llows: verylongerrors counts frames that are 2*maxframesize, dependent on where the maxframesize variable is set. if maxframesize sets greater than half of the available count in rxoctetsbad (2^14-1), verylongerrors is never incremented, but longerrors is incremented. this is due to a limitation in the counter size, which means that an accurate count will not occur in the rxoctetsbad counter if the frame is larger than 2^14-1. maxframesize is determined by the settings in the ?max frame size register (addr: port_index + 0x0f)? on page 104 .
intel ? ixf1110 10-port gigabit ethernet media access controller 114 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 6.5.3 mac tx statistics register overview the mac tx statistics registers contain all the mac transmit statistic counters and are cleared when read. the software must poll these registers to accumulate valu es and ensure that the counters do not wrap. the 32-bit counters wrap after approximately 30 seconds. table 64 covers the mac tx statistics registers for all 10 mac ports. the address is identical to the port number. table 64. mac tx statistics registers (addr: port_index + 0x40 - port_index + 0x58) name description address type 1 default txoctetstotalok counts the bytes transmitted in all legal frames. the count includes all bytes from the destination mac address to and including the crc. the initial preamble and sfd bytes are not counted. port_index + 0x40 rr 0x00000000 txoctetsbad counts the bytes transmitted in all bad frames. the count includes all bytes from the destination mac address to and including the crc. the initial preamble and sfd bytes are not counted. tx underrun counted: the count is expected to match the number of bytes actually transmitted before the frame is discarded. tx crc error counted: all bytes not sent with success are counted by this counter port_index + 0x41 rr 0x00000000 txucpkts the total number of unicast packets transmitted (excluding bad packets) port_index + 0x42 rr 0x00000000 txmcpkts the total number of multicast packets transmitted (excluding bad packets) note: this count includes pause control packets which are also counted in the txpauseframes counter. thus, these types of packets are counted twice. take care when summing register counts for reporting mib information. port_index + 0x43 rr 0x00000000 txbcpkts the total number of broadcast packets transmitted (excluding bad packets) port_index + 0x44 rr 0x00000000 txpkts64octets the total number of packets transmitted (including bad packets) that were 64 octets in length. incremented for tagged packets with a length of 64 bytes, including tag field port_index + 0x45 rr 0x00000000 txpkts65to127octets the total number of packets transmitted (including bad packets) that were [65-127] octets in length. incremented for tagged packets with a length of 65 - 127 bytes, including tag field port_index + 0x46 rr 0x00000000 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 115 document #: 250210 revision #: 004 rev. date: december 18, 2002 txpkts128to255octets the total number of packets transmitted (including bad packets) that were [128-255] octets in length. incremented for tagged packets with a length of 128 - 255 bytes, including tag field port_index + 0x47 rr 0x00000000 txpkts256to511octets the total number of packets transmitted (including bad packets) that were [256-511] octets in length. incremented for tagged packets with a length of 256 - 511 bytes, including tag field port_index + 0x48 rr 0x00000000 txpkts512to1023octets the total number of packets transmitted (including bad packets) that were [512 - 1023] octets in length. incremented for tagged packets with a length of 512 - 1023 bytes, including tag field port_index + 0x49 rr 0x00000000 txpkts1024to1518octets the total number of packets transmitted (including bad packets) that were [1024-1518] octets in length. incremented for tagged packet with a length between 1024-1522, including the tag port_index + 0x4a rr 0x00000000 txpkts1519tomaxoctets the total number of packets transmitted (including bad packets) that were >1518 octets in length. incremented for tagged packet with a length between 1523-max frame size, including the tag port_index + 0x4b rr 0x00000000 txdeferred number of times the initial transmission attempt of a frame is postponed due to another frame already being transmitted on the ethernet network. note : n/a - half-duplex only port_index + 0x4c rr 0x00000000 txtotalcollisions sum of all collision events note : n/a - half-duplex only port_index + 0x4d rr 0x00000000 txsinglecollisions a count of successfully transmitted frames on a particular interface where the transmission is inhibited by exactly one collision. a frame that is counted by an instance of this object is also counted by the corresponding instance of either the unicastpkts, multicastpkts, or broadcastpkts, and is not counted by the corresponding instance of the multiplecollisionframes object. note : n/a - half-duplex only port_index + 0x4e rr 0x00000000 table 64. mac tx statistics registers (addr: port_index + 0x40 - port_index + 0x58) name description address type 1 default 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 116 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 txmultiplecollisions a count of successfully transmitted frames on a particular interface for which transmission is inhibited by more than one collision. a frame that is counted by an instance of this object is also counted by the corresponding instance of either the unicastpkts, multicastpkts, or broadcastpkts, and is not counted by the corresponding instance of the singlecollisionframes object. note : n/a - half-duplex only port_index + 0x4f rr 0x00000000 txlatecollisions the number of times a collision is detected on a particular interface later than 512 bit-times into the transmission of a packet. such frame are terminated and discarded. note : n/a - half-duplex only port_index + 0x50 rr 0x00000000 txexcessivecollisionerrors a count of frames, which collides 16 times and is then discarded by the mac. not effecting xmultiplecollisions note: n/a - half-duplex only port_index + 0x51 rr 0x00000000 txexcessivedeferralerrors number of times frame transmission is postponed more than 2*maxframesize due to another frame already being transmitted on the ethernet network. this causes the mac to discard the frame. note : n/a - half-duplex only port_index + 0x52 rr 0x00000000 txexcessivelengthdrop frame transmissions aborted by the mac because the frame is longer than maximum frame size. these frames are truncated by the mac when the maximum frame size violation is detected by the mac. port_index + 0x53 rr 0x00000000 txunderrun internal tx error which causes the mac to end the transmission before the end of the frame because the mac did not get the needed data in time for transmission. the frames are lost and a fragment or a crc error is transmitted. port_index + 0x54 rr 0x00000000 txtagged number of ok frames with vlan tag. (type field = 0x8100). port_index + 0x55 rr 0x00000000 table 64. mac tx statistics registers (addr: port_index + 0x40 - port_index + 0x58) name description address type 1 default 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 117 document #: 250210 revision #: 004 rev. date: december 18, 2002 txcrcerror number of frames transmitted with a legal size, but with the wrong crc field (also called fcs field) port_index + 0x56 rr 0x00000000 txpauseframes number of pause mac frames transmitted port_index + 0x57 rr 0x00000000 txflowcontrolcollisions send collisions generated on purpose on incoming frames, to avoid reception of traffic, while the port is in half-duplex and has flow control enabled, and do not have sufficient memory to receive more frames. note: due to the internal counting technique, a last frame might have to be transmitted after last flow control collision send to get the correct statistic. note : n/a - half-duplex only port_index + 0x58 rr 0x00000000 table 64. mac tx statistics registers (addr: port_index + 0x40 - port_index + 0x58) name description address type 1 default 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 118 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 6.5.4 global status and conf iguration register overview table 65 through table 70 on page 121 provide an overview of the global control and status registers. table 65. port enable register (addr: 0x500) bit name description type 1 default register description: a control register for each port in the ixf1110. port id = bit position in the register. to make a port active, the bit must be set high (for example, port 4 active implies register value = 0001.0000). setting the bit to 0 disables the port. the default state for this register is for all 10 ports to be active. 0x000003ff 31:10 reserved reserved ro 0x00000 9 port 9 enable port 9 0 = disable 1 = enable r/w 1 8 port 8 enable port 8 0 = disable 1 = enable r/w 1 7 port 7 enable port 7 0 = disable 1 = enable r/w 1 6 port 6 enable port 6 0 = disable 1 = enable r/w 1 5 port 5 enable port 5 0 = disable 1 = enable r/w 1 4 port 4 enable port 4 0 = disable 1 = enable r/w 1 3 port 3 enable port 3 0 = disable 1 = enable r/w 1 2 port 2 enable port 2 0 = disable 1 = enable r/w 1 1 port 1 enable port 1 0 = disable 1 = enable r/w 1 0 port 0 enable port 0 0 = disable 1 = enable r/w 1 1. ro = read only; rr = clear on read; w = write; r/w = read/write 2. if a port is disabled mid-packet on the receive side in serdes mode, the rx stats will not update for that packet due to power-down of serdes when the port is disabled.
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 119 document #: 250210 revision #: 004 rev. date: december 18, 2002 table 66. link led enable register (addr: 0x502) bit name description type 1 default register description: per-port bit should be set upon detection of link to enable proper operation of the link leds. 0x00000000 31:10 reserved reserved ro 0x00000 9 link led enable port 9 port 9 link 0 = no link 1 = link r/w 0 8 link led enable port 8 port 8 link 0 = no link 1 = link r/w 0 7 link led enable port 7 port 7 link 0 = no link 1 = link r/w 0 6 link led enable port 6 port 6 link 0 = no link 1 = link r/w 0 5 link led enable port 5 port 5 link 0 = no link 1 = link r/w 0 4 link led enable port 4 port 4 link 0 = no link 1 = link r/w 0 3 link led enable port 3 port 3 link 0 = no link 1 = link r/w 0 2 link led enable port 2 port 2 link 0 = no link 1 = link r/w 0 1 link led enable port 1 port 1 link 0 = no link 1 = link r/w 0 0 link led enable port 0 port 0 link 0 = no link 1 = link r/w 0 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 120 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 table 67. cpu interface register (addr: 0x508) bit name description type 1 default register description: cpu interface endian select. this register allows the user to select the endian of the cpu interface to allow various different cpus to be connected to the ixf1110. 0x00000000 31:1 reserved reserved ro 0x00000000 0 endian 0 = little endian 1 = big endian r/w 0 1. ro = read only; rr = clear on read; w = write; r/w = read/write table 68. led control register (addr: 0x509) bit name description type 1 default register description: globally selects and enables the led mode. 0x00000000 31-2 reserved reserved ro 0x00000000 1 led enable 0 = 1 = disable leds enable leds r/w 0 0 led_sel_mode 0 = 1 = enable led mode 0 for use with sgs thompson m5450 led driver (default) led mode 1 for use with standard octal shift register r/w 0 1. ro = read only; rr = clear on read; w = write; r/w = read/write table 69. led flash rate register (addr: 0x50a) bit name description type 1 default register description: globally selects and enables the flash rate. 0x00000000 31:3 reserved reserved ro 0x00000000 2:0 led flash rate 000 = 100 ms flash rate 001 = 200 ms flash rate 010 = 300 ms flash rate 011 = 400 ms flash rate 100 = 500 ms flash rate 101 = reserved 110 = reserved 111 = reserved r/w 000 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 121 document #: 250210 revision #: 004 rev. date: december 18, 2002 table 70. led fault disabl e register (addr: 0x50b) bit name description type 1 default register description: per-port fault disable: disables the led flashing for local or remote faults 0x00000000 31:10 reserved reserved ro 0x000000 9 led fault disable port 9 port 9 0 = fault enabled 1 = fault disabled r/w 0 8 led fault disable port 8 port 8 0 = fault enabled 1 = fault disabled r/w 0 7 led fault disable port 7 port 7 0 = fault enabled 1 = fault disabled r/w 0 6 led fault disable port 6 port 6 0 = fault enabled 1 = fault disabled r/w 0 5 led fault disable port 5 port 5 0 = fault enabled 1 = fault disabled r/w 0 4 led fault disable port 4 port 4 0 = fault enabled 1 = fault disabled r/w 0 3 led fault disable port 3 port 3 0 = fault enabled 1 = fault disabled r/w 0 2 led fault disable port 2 port 2 0 = fault enabled 1 = fault disabled r/w 0 1 led fault disable port 1 port 1 0 = fault enabled 1 = fault disabled r/w 0 0 led fault disable port 0 port 0 0 = fault enabled 1 = fault disabled r/w 0 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 122 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 table 71. jtag id revision register (addr: 0x50c) bit name description type default register description: the value of this register follows the same scheme as the device identification register found in the ieee 1149.1 specification. the upper 4 bits correspond to silicon stepping. the next 16 bits store a part id number. the next 11 bits contain a jedec manufacturer id. bit zero = 1 if the chip is the first in a stack. the encoding scheme used for the product id field is implementation dependent. 0x20456013 31:28 version version ro 0010 27:12 part id part id ro 0000010001010110 11:8 jedec cont. jedec cont. ro 0000 7:1 jedec id jedec id ro 0001001 0 reserved reserved ro 1 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 123 document #: 250210 revision #: 004 rev. date: december 18, 2002 6.5.5 global rx bloc k register overview table 72 through table 76 on page 129 provide an overview of the rx block registers, which include the rx fifo hi gh and low watermarks. table 72. rx fifo high watermark ports 0 to 9 registers (addr: 0x580 - 0x589) name 2 description address type 1 default rx fifo high watermark port 0 high watermark for rx fifo port 0. the default value is 1856 bytes. when the amount of data stored in the fifo exceeds this value, a flow control command is sent to the corresponding tx mac. 0x580 r/w 0x00000740 rx fifo high watermark port 1 high watermark for rx fifo port 1. the default value is 1856 bytes. when the amount of data stored in the fifo exceeds this value, a flow control command is sent to the corresponding tx mac. 0x581 r/w 0x00000740 rx fifo high watermark port 2 high watermark for rx fifo port 2. the default value is 1856 bytes. when the amount of data stored in the fifo exceeds this value, a flow control command is sent to the corresponding tx mac. 0x582 r/w 0x00000740 rx fifo high watermark port 3 high watermark for rx fifo port 3. the default value is 1856 bytes. when the amount of data stored in the fifo exceeds this value, a flow control command is sent to the corresponding tx mac. 0x583 r/w 0x00000740 rx fifo high watermark port 4 high watermark for rx fifo port 4. the default value is 1856 bytes. when the amount of data stored in the fifo exceeds this value, a flow control command is sent to the corresponding tx mac. 0x584 r/w 0x00000740 rx fifo high watermark port 5 high watermark for rx fifo port 5. the default value is 1856 bytes. when the amount of data stored in the fifo exceeds this value, a flow control command is sent to the corresponding tx mac. 0x585 r/w 0x00000740 rx fifo high watermark port 6 high watermark for rx fifo port 6. the default value is 1856 bytes. when the amount of data stored in the fifo exceeds this value, a flow control command is sent to the corresponding tx mac. 0x586 r/w 0x00000740 1. ro = read only; rr = clear on read; w = write; r/w = read/write 2. for all rx fifo high watermark registers, the following bit definitions apply to all ports (0:9): bits 31:15 - reserved and ro. bits 14:0 - described above.
intel ? ixf1110 10-port gigabit ethernet media access controller 124 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 rx fifo high watermark port 7 high watermark for rx fifo port 7. the default value is 1856 bytes. when the amount of data stored in the fifo exceeds this value, a flow control command is sent to the corresponding tx mac. 0x587 r/w 0x00000740 rx fifo high watermark port 8 high watermark for rx fifo port 8. the default value is 1856 bytes. when the amount of data stored in the fifo exceeds this value, a flow control command is sent to the corresponding tx mac 0x588 r/w 0x00000740 rx fifo high watermark port 9 high watermark for rx fifo port 9. the default value is 1856 bytes. when the amount of data stored in the fifo exceeds this value, a flow control command is sent to the corresponding tx mac. 0x589 r/w 0x00000740 table 73. rx fifo low watermark ports 0 to 9 registers (addr: 0x58a - 0x593) name 2 description address type 1 default rx fifo low watermark port 0 low watermark for rx fifo port 0. the default value is 1840 bytes. when the port is in flow control, and the amount of data stored in the fifo goes below this value, the flow control command is terminated in the corresponding tx mac. 0x58a r/w 0x00000730 rx fifo low watermark port 1 low watermark for rx fifo port 1. the default value is 1840 bytes. when the port is in flow control and the amount of data stored in the fifo goes below this value, the flow control command is terminated in the corresponding tx mac. 0x58b r/w 0x00000730 rx fifo low watermark port 2 low watermark for rx fifo port 2. the default value is 1840 bytes. when the port is in flow control and the amount of data stored in the fifo goes below this value, the flow control command is terminated in the corresponding tx mac. 0x58c r/w 0x00000730 rx fifo low watermark port 3 low watermark for rx fifo port 3. the default value is 1840 bytes. when the port is in flow control and the amount of data stored in the fifo goes below this value, the flow control command is terminated in the corresponding tx mac. 0x58d r/w 0x00000730 rx fifo low watermark port 4 low watermark for rx fifo port 4. the default value is 1840 bytes. when the port is in flow control and the amount of data stored in the fifo goes below this value, the flow control command is terminated in the corresponding tx mac. 0x58e r/w 0x00000730 1. ro = read only; rr = clear on read; w = write; r/w = read/write 2. for all rx fifo low watermark registers, the fo llowing bit definitions apply to all ports (0:9): bits 31:15 - reserved and ro. bits 14:0 - described above. table 72. rx fifo high watermark ports 0 to 9 registers (addr: 0x580 - 0x589) (continued) name 2 description address type 1 default 1. ro = read only; rr = clear on read; w = write; r/w = read/write 2. for all rx fifo high watermark registers, the following bit definitions apply to all ports (0:9): bits 31:15 - reserved and ro. bits 14:0 - described above.
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 125 document #: 250210 revision #: 004 rev. date: december 18, 2002 rx fifo low watermark port 5 low watermark for rx fifo port 5. the default value is 1840 bytes. when the port is in flow control and the amount of data stored in the fifo goes below this value, the flow control command is terminated in the corresponding tx mac. 0x58f r/w 0x00000730 rx fifo low watermark port 6 low watermark for rx fifo port 6. the default value is 1840 bytes. when the port is in flow control and the amount of data stored in the fifo goes below this value, the flow control command is terminated in the corresponding tx mac. 0x590 r/w 0x00000730 rx fifo low watermark port 7 low watermark for rx fifo port 7. the default value is 1840 bytes.when the port is in flow control and the amount of data stored in the fifo goes below this value, the flow control command is terminated in the corresponding tx mac. 0x591 r/w 0x00000730 rx fifo low watermark port 8 low watermark for rx fifo port 8. the default value is 1840 bytes. when the port is in flow control and the amount of data stored in the fifo goes below this value, the flow control command is terminated in the corresponding tx mac. 0x592 r/w 0x00000730 rx fifo low watermark port 9 low watermark for rx fifo port 9. the default value is 1840 bytes. when the port is in flow control and the amount of data stored in the fifo goes below this value, the flow control command is terminated in the corresponding tx mac. 0x593 r/w 0x00000730 table 73. rx fifo low watermark ports 0 to 9 registers (addr: 0x58a - 0x593) (continued) name 2 description address type 1 default 1. ro = read only; rr = clear on read; w = write; r/w = read/write 2. for all rx fifo low watermark registers, the following bit definitions apply to all ports (0:9): bits 31:15 - reserved and ro. bits 14:0 - described above.
intel ? ixf1110 10-port gigabit ethernet media access controller 126 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 table 74. rx fifo number of frames removed ports 0 to 9 registers (addr: 0x594 - 0x59d) name 2 description address type 1 default rx fifo number of frames removed on port 0 this register counts all frames removed from the rx fifo for port 0 by meeting one of the following conditions: ? the rx fifo on this port becomes full ? frames are removed in conjunction with the rx fifo errored frame drop enable register ( table 75 on page 128 ) ? frames are greater than the maxframesize ( table 53 on page 104 ) 0x594 rr 0x00000000 rx fifo number of frames removed on port 1 this register counts all frames removed from the rx fifo for port 1 by meeting one of the following conditions: ? the rx fifo on this port becomes full ? frames are removed in conjunction with the rx fifo errored frame drop enable register ( table 75 on page 128 ) ? frames are greater than the maxframesize ( table 53 on page 104 ) 0x595 rr 0x00000000 rx fifo number of frames removed on port 2 this register counts all frames removed from the rx fifo for port 2 by meeting one of the following conditions: ? the rx fifo on this port becomes full ? frames are removed in conjunction with the rx fifo errored frame drop enable register ( table 75 on page 128 ) ? frames are greater than the maxframesize ( table 53 on page 104 ) 0x596 rr 0x00000000 rx fifo number of frames removed on port 3 this register counts all frames removed from the rx fifo for port 3 by meeting one of the following conditions: ? the rx fifo on this port becomes full ? frames are removed in conjunction with the rx fifo errored frame drop enable register ( table 75 on page 128 ) ? frames are greater than the maxframesize ( table 53 on page 104 ) 0x597 rr 0x00000000 rx fifo number of frames removed on port 4 this register counts all frames removed from the rx fifo for port 4 by meeting one of the following conditions: ? the rx fifo on this port becomes full ? frames are removed in conjunction with the rx fifo errored frame drop enable register ( table 75 on page 128 ) ? frames are greater than the maxframesize ( table 53 on page 104 ) 0x598 rr 0x00000000 1. ro = read only; rr = clear on read; w = write; r/w = read/write. 2. for all number of frames removed registers, t he following bit definitions apply to all ports (0:9): bits 31:22 - reserved and ro. bits 21:0 - described above.
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 127 document #: 250210 revision #: 004 rev. date: december 18, 2002 rx fifo number of frames removed on port 5 this register counts all frames removed from the rx fifo for port 5 by meeting one of the following conditions: ? the rx fifo on this port becomes full ? frames are removed in conjunction with the rx fifo errored frame drop enable register ( table 75 on page 128 ) ? frames are greater than the maxframesize ( table 53 on page 104 ) 0x599 rr 0x00000000 rx fifo number of frames removed on port 6 this register counts all frames removed from the rx fifo for port 6 by meeting one of the following conditions: ? the rx fifo on this port becomes full ? frames are removed in conjunction with the rx fifo errored frame drop enable register ( table 75 on page 128 ) ? frames are greater than the maxframesize ( table 53 on page 104 ) 0x59a rr 0x00000000 rx fifo number of frames removed on port 7 this register counts all frames removed from the rx fifo for port 7 by meeting one of the following conditions: ? the rx fifo on this port becomes full ? frames are removed in conjunction with the rx fifo errored frame drop enable register ( table 75 on page 128 ) ? frames are greater than the maxframesize ( table 53 on page 104 ) 0x59b rr 0x00000000 rx fifo number of frames removed on port 8 this register counts all frames removed from the rx fifo for port 8 by meeting one of the following conditions: ? the rx fifo on this port becomes full ? frames are removed in conjunction with the rx fifo errored frame drop enable register ( table 75 on page 128 ) ? frames are greater than the maxframesize ( table 53 on page 104 ) 0x59c rr 0x00000000 rx fifo number of frames removed on port 9 this register counts all frames removed from the rx fifo for port 9 by meeting one of the following conditions: ? the rx fifo on this port becomes full ? frames are removed in conjunction with the rx fifo errored frame drop enable register ( table 75 on page 128 ) ? frames are greater than the maxframesize ( table 53 on page 104 ) 0x59d rr 0x00000000 table 74. rx fifo number of frames removed ports 0 to 9 registers (addr: 0x594 - 0x59d) name 2 description address type 1 default 1. ro = read only; rr = clear on read; w = write; r/w = read/write. 2. for all number of frames removed registers, the following bit definitions apply to all ports (0:9): bits 31:22 - reserved and ro. bits 21:0 - described above.
intel ? ixf1110 10-port gigabit ethernet media access controller 128 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 table 75. rx fifo errored frame drop enable register (addr: 0x59f) bit name description type 1 default register description: this register is used in conjunction with the rx packet filter control register bits to select whether errored or filtered frames are to be dropped. 0x00000000 31:10 reserved reserved ro 0x000000 9 rx fifo errored frame drop enable port 9 these bits are used in conjunction with the ?rx packet filter control register (addr: port_index + 0x19)? bits, allowing the user to select whether errored or filtered frames are to be dropped or not. port 9: 0 = do not drop frames 1 = drop frames r/w 0 8 rx fifo errored frame drop enable port 8 these bits are used in conjunction with the ?rx packet filter control register (addr: port_index + 0x19)? bits, allowing the user to select whether errored or filtered frames are to be dropped or not. port 8: 0 = do not drop frames 1 = drop frames r/w 0 7 rx fifo errored frame drop enable port 7 these bits are used in conjunction with the ?rx packet filter control register (addr: port_index + 0x19)? bits, allowing the user to select whether errored or filtered frames are to be dropped or not. port 7: 0 = do not drop frames 1 = drop frames r/w 0 6 rx fifo errored frame drop enable port 6 these bits are used in conjunction with the ?rx packet filter control register (addr: port_index + 0x19)? bits, allowing the user to select whether errored or filtered frames are to be dropped or not. port 6: 0 = do not drop frames 1 = drop frames r/w 0 5 rx fifo errored frame drop enable port 5 these bits are used in conjunction with the ?rx packet filter control register (addr: port_index + 0x19)? bits, allowing the user to select whether errored or filtered frames are to be dropped or not. port 5: 0 = do not drop frames 1 = drop frames r/w 0 4 rx fifo errored frame drop enable port 4 these bits are used in conjunction with the ?rx packet filter control register (addr: port_index + 0x19)? bits, allowing the user to select whether errored or filtered frames are to be dropped or not. port 4: 0 = do not drop frames 1 = drop frames r/w 0 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 129 document #: 250210 revision #: 004 rev. date: december 18, 2002 3 rx fifo errored frame drop enable port 3 these bits are used in conjunction with the ?rx packet filter control register (addr: port_index + 0x19)? bits, allowing the user to select whether errored or filtered frames are to be dropped or not. port 3: 0 = do not drop frames 1 = drop frames r/w 0 2 rx fifo errored frame drop enable port 2 these bits are used in conjunction with the ?rx packet filter control register (addr: port_index + 0x19)? bits, allowing the user to select whether errored or filtered frames are to be dropped or not. port 2: 0 = do not drop frames 1 = drop frames r/w 0 1 rx fifo errored frame drop enable port 1 these bits are used in conjunction with the ?rx packet filter control register (addr: port_index + 0x19)? bits, allowing the user to select whether errored or filtered frames are to be dropped or not. port 1: 0 = do not drop frames 1 = drop frames r/w 0 0 rx fifo errored frame drop enable port 0 these bits are used in conjunction with the ?rx packet filter control register (addr: port_index + 0x19)? bits, allowing the user to select whether errored or filtered frames are to be dropped or not. port 0: 0 = do not drop frames 1 = drop frames r/w 0 table 76. rx fifo overflow event register (addr: 0x5a0) bit name description type 1 default register description: this register provides a status if a fifo-full situation has occurred (for example, a fifo overflow). the bit position equals the port number. this register is cleared on read. 0x00000000 31:10 reserved reserved ro 0x000000 9 rx fifo overflow event port 9 port 9 1 = fifo overflow event occurred 0 = fifo overflow event did not occur rr 0 8 rx fifo overflow event port 8 port 8 1 = fifo overflow event occurred 0 = fifo overflow event did not occur rr 0 7 rx fifo overflow event port 7 port 7 1 = fifo overflow event occurred 0 = fifo overflow event did not occur rr 0 1. ro = read only; rr = clear on read; w = write; r/w = read/write table 75. rx fifo errored frame drop enable register (addr: 0x59f) (continued) bit name description type 1 default 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 130 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 6 rx fifo overflow event port 6 port 6 1 = fifo overflow event occurred 0 = fifo overflow event did not occur rr 0 5 rx fifo overflow event port 5 port 5 1 = fifo overflow event occurred 0 = fifo overflow event did not occur rr 0 4 rx fifo overflow event port 4 port 4 1 = fifo overflow event occurred 0 = fifo overflow event did not occur rr 0 3 rx fifo overflow event port 3 port 3 1 = fifo overflow event occurred 0 = fifo overflow event did not occur rr 0 2 rx fifo overflow event port 2 port 2 1 = fifo overflow event occurred 0 = fifo overflow event did not occur rr 0 1 rx fifo overflow event port 1 port 1 1 = fifo overflow event occurred 0 = fifo overflow event did not occur rr 0 0 rx fifo overflow event port 0 port 0 1 = fifo overflow event occurred 0 = fifo overflow event did not occur rr 0 table 76. rx fifo overflow even t register (addr: 0x5a0) (continued) bit name description type 1 default 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 131 document #: 250210 revision #: 004 rev. date: december 18, 2002 6.5.6 tx block register overview table 77 through table 82 on page 139 provide an overview of the tx block registers, which include the tx fifo high and low watermark. table 77. tx fifo high watermark ports 0 to 9 (addr: 0x600 - 0x609) name 2 description address type 1 default tx fifo high watermark port 0 high watermark for tx fifo port 0. the default value is 1584 bytes. when the amount of data stored in the fifo exceeds this value, the tx fifo indicates ?satis fied.? this implies further up in the system that no more data must be sent to this port. 0x600 r/w 0x00000630 tx fifo high watermark port 1 high watermark for tx fifo port 1. the default value is 1584 bytes. when the amount of data stored in the fifo exceeds this value, the tx fifo indicates ?satis fied.? this implies further up in the system that no more data must be sent to this port. 0x601 r/w 0x00000630 tx fifo high watermark port 2 high watermark for tx fifo port 2. the default value is 1584 bytes. when the amount of data stored in the fifo exceeds this value, the tx fifo indicates ?satis fied.? this implies further up in the system that no more data must be sent to this port. 0x602 r/w 0x00000630 tx fifo high watermark port 3 high watermark for tx fifo port 3. the default value is 1584 bytes. when the amount of data stored in the fifo exceeds this value, the tx fifo indicates ?satis fied.? this implies further up in the system that no more data must be sent to this port. 0x603 r/w 0x00000630 tx fifo high watermark port 4 high watermark for tx fifo port 4. the default value is 1584 bytes. when the amount of data stored in the fifo exceeds this value, the tx fifo indicates ?satis fied.? this implies further up in the system that no more data must be sent to this port. 0x604 r/w 0x00000630 tx fifo high watermark port 5 high watermark for tx fifo port 5. the default value is 1584 bytes. when the amount of data stored in the fifo exceeds this value, the tx fifo indicates ?satis fied.? this implies further up in the system that no more data must be sent to this port. 0x605 r/w 0x00000630 tx fifo high watermark port 6 high watermark for tx fifo port 6. the default value is 1584 bytes. when the amount of data stored in the fifo exceeds this value, the tx fifo indicates ?satis fied.? this implies further up in the system that no more data must be sent to this port. 0x606 r/w 0x00000630 1. ro = read only; rr = clear on read; w = write; r/w = read/write 2. for all tx fifo high watermark registers, the following bit definitions apply to all ports (0:9): bits 31:13 - reserved and ro. bits 12:0 - described above.
intel ? ixf1110 10-port gigabit ethernet media access controller 132 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 tx fifo high watermark port 7 high watermark for tx fifo port 7. the default value is 1584 bytes. when the amount of data stored in the fifo exceeds this value, the tx fifo indicates ?satisfied.? this implies further up in the system that no more data must be sent to this port. 0x607 r/w 0x00000630 tx fifo high watermark port 8 high watermark for tx fifo port 8. the default value is 1584 bytes. when the amount of data stored in the fifo exceeds this value, the tx fifo indicates ?satisfied.? this implies further up in the system that no more data must be sent to this port. 0x608 r/w 0x00000630 tx fifo high watermark port 9 high watermark for tx fifo port 9. the default value is 1584 bytes. when the amount of data stored in the fifo exceeds this value, the tx fifo indicates ?satisfied.? this implies further up in the system that no more data must be sent to this port. 0x609 r/w 0x00000630 table 78. tx fifo low watermark ports 0 to 9 (addr: 0x60a - 0x613) name 2 description address type 1 default tx fifo low watermark port 0 low watermark for tx fifo port 0. the default value is 464 bytes. when the amount of data falls below this value, the tx fifo status indicates ?starving?. this implies further up in the system that more data must be sent to this port to prevent an underrun. 0x60a r/w 0x000001d0 tx fifo low watermark port 1 low watermark for tx fifo port 1. the default value is 464 bytes. when the amount of data falls below this value, the tx fifo status indicates ?starving?. this implies further up in the system that more data must be sent to this port to prevent an underrun. 0x60b r/w 0x000001d0 tx fifo low watermark port 2 low watermark for tx fifo port 2. the default value is 464 bytes. when the amount of data falls below this value, the tx fifo status indicates ?starving?. this implies further up in the system that more data must be sent to this port to prevent an underrun. 0x60c r/w 0x000001d0 tx fifo low watermark port 3 low watermark for tx fifo port 3. the default value is 464 bytes. when the amount of data falls below this value, the tx fifo status indicates ?starving?. this implies further up in the system that more data must be sent to this port to prevent an underrun. 0x60d r/w 0x000001d0 1. ro = read only; rr = clear on read; w = write; r/w = read/write 2. for all tx fifo low watermark registers, the following bit definitions apply to all ports (0:9): bits 31:13 - reserved and ro. bits 12:0 - described above. table 77. tx fifo high watermark ports 0 to 9 (addr: 0x600 - 0x609) (continued) name 2 description address type 1 default 1. ro = read only; rr = clear on read; w = write; r/w = read/write 2. for all tx fifo high watermark registers, the following bit definitions apply to all ports (0:9): bits 31:13 - reserved and ro. bits 12:0 - described above.
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 133 document #: 250210 revision #: 004 rev. date: december 18, 2002 tx fifo low watermark port 4 low watermark for tx fifo port 4. the default value is 464 bytes. when the amount of data falls below this value, the tx fifo status indicates ?starving?. this implies further up in the system that more data must be sent to this port to prevent an underrun. 0x60e r/w 0x000001d0 tx fifo low watermark port 5 low watermark for tx fifo port 5. the default value is 464 bytes. when the amount of data falls below this value, the tx fifo status indicates ?starving?. this implies further up in the system that more data must be sent to this port to prevent an underrun. 0x60f r/w 0x000001d0 tx fifo low watermark port 6 low watermark for tx fifo port 6. the default value is 464 bytes. when the amount of data falls below this value, the tx fifo status indicates ?starving?. this implies further up in the system that more data must be sent to this port to prevent an underrun. 0x610 r/w 0x000001d0 tx fifo low watermark port 7 low watermark for tx fifo port 7. the default value is 464 bytes. when the amount of data falls below this value, the tx fifo status indicates ?starving?. this implies further up in the system that more data must be sent to this port to prevent an underrun. 0x611 r/w 0x000001d0 tx fifo low watermark port 8 low watermark for tx fifo port 8. the default value is 464 bytes. when the amount of data falls below this value, the tx fifo status indicates ?starving?. this implies further up in the system that more data must be sent to this port to prevent an underrun. 0x612 r/w 0x000001d0 tx fifo low watermark port 9 low watermark for tx fifo port 9. the default value is 464 bytes. when the amount of data falls below this value, the tx fifo status indicates ?starving?. this implies further up in the system that more data must be sent to this port to prevent an underrun. 0x613 r/w 0x000001d0 table 78. tx fifo low watermark ports 0 to 9 (addr: 0x60a - 0x613) (continued) name 2 description address type 1 default 1. ro = read only; rr = clear on read; w = write; r/w = read/write 2. for all tx fifo low watermark registers, the following bit definitions apply to all ports (0:9): bits 31:13 - reserved and ro. bits 12:0 - described above.
intel ? ixf1110 10-port gigabit ethernet media access controller 134 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 table 79. tx fifo mac transfer threshold ports 0 to 9 (addr: 0x614 - 0x61d) name 2 description 3 address type 1 default tx fifo mac transfer threshold port 0 sets the value at which the fifo begins to transfer data to the mac. the bottom 3 bits of this register are ignored, and the threshold is set in increments of 8-byte steps. if this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the fifo only are allowed. transfer begins when either the count value in this register is exceeded or an end-of-frame is received. 0x614 r/w 0x00000100 tx fifo mac transfer threshold port 1 sets the value at which the fifo begins to transfer data to the mac. the bottom 3 bits of this register are ignored, and the threshold is set in increments of 8-byte steps. if this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the fifo only are allowed. transfer begins when either the count value in this register is exceeded or an end-of-frame is received. 0x615 r/w 0x00000100 tx fifo mac transfer threshold port 2 sets the value at which the fifo begins to transfer data to mac. the bottom 3 bits of this register are ignored, thus the threshold is set in increments of 8 byte steps. if this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the fifo only are allowed. transfer begins when either the count value in this register is exceeded or an end-of-frame is received. 0x616 r/w 0x00000100 tx fifo mac transfer threshold port 3 sets the value at which the fifo begins to transfer data to mac. the bottom 3 bits of this register are ignored, thus the threshold is set in increments of 8 byte steps. if this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the fifo only are allowed. transfer begins when either the count value in this register is exceeded or an end-of-frame is received. 0x617 r/w 0x00000100 1. ro = read only; rr = clear on read; w = write; r/w = read/write 2. for all mac transfer threshold registers, the fo llowing bit definitions apply to all ports (0:9): bits 31:13 - reserved and ro. bits 12:0 - described above. 3. for proper operation of the ixf1110, the mac transfer threshold must be set to greater than the maxburst1 on the spi4-2.
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 135 document #: 250210 revision #: 004 rev. date: december 18, 2002 tx fifo mac transfer threshold port 4 sets the value at which the fifo begins to transfer data to mac. the bottom 3 bits of this register are ignored, thus the threshold is set in increments of 8 byte steps. if this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the fifo only are allowed. transfer begins when either the count value in this register is exceeded or an end-of-frame is received. 0x618 r/w 0x00000100 tx fifo mac transfer threshold port 5 sets the value at which the fifo begins to transfer data to mac. the bottom 3 bits of this register are ignored, thus the threshold is set in increments of 8 byte steps. if this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the fifo only are allowed. transfer begins when either the count value in this register is exceeded or an end-of-frame is received. 0x619 r/w 0x00000100 tx fifo mac transfer threshold port 6 sets the value at which the fifo begins to transfer data to mac. the bottom 3 bits of this register are ignored, thus the threshold is set in increments of 8 byte steps. if this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the fifo only are allowed. transfer begins when either the count value in this register is exceeded or an end-of-frame is received. 0x61a r/w 0x00000100 tx fifo mac transfer threshold port 7 sets the value at which the fifo begins to transfer data to mac. the bottom 3 bits of this register are ignored, thus the threshold is set in increments of 8 byte steps. if this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the fifo only are allowed. transfer begins when either the count value in this register is exceeded or an end-of-frame is received. 0x61b r/w 0x00000100 table 79. tx fifo mac transfer threshold po rts 0 to 9 (addr: 0x614 - 0x61d) (continued) name 2 description 3 address type 1 default 1. ro = read only; rr = clear on read; w = write; r/w = read/write 2. for all mac transfer threshold registers, the following bit definitions apply to all ports (0:9): bits 31:13 - reserved and ro. bits 12:0 - described above. 3. for proper operation of the ixf1110, the mac transfer threshold must be set to greater than the maxburst1 on the spi4-2.
intel ? ixf1110 10-port gigabit ethernet media access controller 136 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 tx fifo mac transfer threshold port 8 sets the value at which the fifo begins to transfer data to the mac. the bottom 3 bits of this register are ignored, thus the threshold is set in increments of 8 byte steps. if this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the fifo only are allowed. transfer begins when either the count value in this register is exceeded or an end-of-frame is received. 0x61c r/w 0x00000100 tx fifo mac transfer threshold port 9 sets the value at which the fifo begins to transfer data to the mac. the bottom 3 bits of this register are ignored, thus the threshold is set in increments of 8 byte steps. if this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the fifo only are allowed. transfer begins when either the count value in this register is exceeded or an end-of-frame is received. 0x61d r/w 0x00000100 table 79. tx fifo mac transfer threshold ports 0 to 9 (addr: 0x614 - 0x61d) (continued) name 2 description 3 address type 1 default 1. ro = read only; rr = clear on read; w = write; r/w = read/write 2. for all mac transfer threshold registers, the fo llowing bit definitions apply to all ports (0:9): bits 31:13 - reserved and ro. bits 12:0 - described above. 3. for proper operation of the ixf1110, the mac transfer threshold must be set to greater than the maxburst1 on the spi4-2.
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 137 document #: 250210 revision #: 004 rev. date: december 18, 2002 table 80. tx fifo overflow event register (addr: 0x61e) bit name description type 1 default register description: this register provides status that a fi fo- full situation has occurred (for example, a fifo overflow). the bit position equals the port number. this register is cleared on read. 0x00000000 31:10 reserved reserved ro 0x000000 9 tx fifo overflow event port 9 port 9 1 = fifo overflow event occurred 0 = fifo overflow event did not occur rr 0 8 tx fifo overflow event port 8 port 8 1 = fifo overflow event occurred 0 = fifo overflow event did not occur rr 0 7 tx fifo overflow event port 7 port 7 1 = fifo overflow event occurred 0 = fifo overflow event did not occur rr 0 6 tx fifo overflow event port 6 port 6 1 = fifo overflow event occurred 0 = fifo overflow event did not occur rr 0 5 tx fifo overflow event port 5 port 5 1 = fifo overflow event occurred 0 = fifo overflow event did not occur rr 0 4 tx fifo overflow event port 4 port 4 1 = fifo overflow event occurred 0 = fifo overflow event did not occur rr 0 3 tx fifo overflow event port 3 port 3 1 = fifo overflow event occurred 0 = fifo overflow event did not occur rr 0 2 tx fifo overflow event port 2 port 2 1 = fifo overflow event occurred 0 = fifo overflow event did not occur rr 0 1 tx fifo overflow event port 1 port 1 1 = fifo overflow event occurred 0 = fifo overflow event did not occur rr 0 0 tx fifo overflow event port 0 port 0 1 = fifo overflow event occurred 0 = fifo overflow event did not occur rr 0 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 138 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 table 81. tx fifo info out-of-sequence register (addr: 0x621) bit name description type 1 default register description: this register signals when out-of-s equence data is detected in the tx fifo. events such as sop followed by another sop cause this bit to be set and remain so until read. this register is cleared on read. 0x00000000 31:10 reserved reserved ro 0x000000 9 tx fifo info out-of- sequence port 9 port 9 1 = fifo out-of-sequence event occurred 0 = fifo out-of-sequence event did not occur rr 0 8 tx fifo info out-of- sequence port 8 port 8 1 = fifo out-of-sequence event occurred 0 = fifo out-of-sequence event did not occur rr 0 7 tx fifo info out-of- sequence port 7 port 7 1 = fifo out-of-sequence event occurred 0 = fifo out-of-sequence event did not occur rr 0 6 tx fifo info out-of- sequence port 6 port 6 1 = fifo out-of-sequence event occurred 0 = fifo out-of-sequence event did not occur rr 0 5 tx fifo info out-of- sequence port 5 port 5 1 = fifo out-of-sequence event occurred 0 = fifo out-of-sequence event did not occur rr 0 4 tx fifo info out-of- sequence port 4 port 4 1 = fifo out-of-sequence event occurred 0 = fifo out-of-sequence event did not occur rr 0 3 tx fifo info out-of- sequence port 3 port 3 1 = fifo out-of-sequence event occurred 0 = fifo out-of-sequence event did not occur rr 0 2 tx fifo info out-of- sequence port 2 port 2 1 = fifo out-of-sequence event occurred 0 = fifo out-of-sequence event did not occur rr 0 1 tx fifo info out-of- sequence port 1 port 1 1 = fifo out-of-sequence event occurred 0 = fifo out-of-sequence event did not occur rr 0 0 tx fifo info out-of- sequence port 0 port 0 1 = fifo out-of-sequence event occurred 0 = fifo out-of-sequence event did not occur rr 0 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 139 document #: 250210 revision #: 004 rev. date: december 18, 2002 table 82. tx fifo number of frames removed ports 0-9 (addr: 0x622 - 0x62b) name description address type 1 default tx fifo number of frames removed on port 0 this register counts the number of frames removed on port 0 due to a tx fifo overflow. 0x622 rr 0x00000000 tx fifo number of frames removed on port 1 this register counts the number of frames removed on port 1 due to a tx fifo overflow. 0x623 rr 0x00000000 tx fifo number of frames removed on port 2 this register counts the number of frames removed on port 2 due to a tx fifo overflow. 0x624 rr 0x00000000 tx fifo number of frames removed on port 3 this register counts the number of frames removed on port 3 due to a tx fifo overflow. 0x625 rr 0x00000000 tx fifo number of frames removed on port 4 this register counts the number of frames removed on port 4 due to a tx fifo overflow. 0x626 rr 0x00000000 tx fifo number of frames removed on port 5 this register counts the number of frames removed on port 5 due to a tx fifo overflow. 0x627 rr 0x00000000 tx fifo number of frames removed on port 6 this register counts the number of frames removed on port 6 due to a tx fifo overflow. 0x628 rr 0x00000000 tx fifo number of frames removed on port 7 this register counts the number of frames removed on port 7 due to a tx fifo overflow. 0x629 rr 0x00000000 tx fifo number of frames removed on port 8 this register counts the number of frames removed on port 8 due to a tx fifo overflow. 0x62a rr 0x00000000 tx fifo number of frames removed on port 9 this register counts the number of frames removed on port 9 due to a tx fifo overflow. 0x62b rr 0x00000000 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 140 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 6.5.7 spi4-2 block register overview table 83 through table 86 on page 142 provide an overview of the spi4-2 block registers. table 83. spi4-2 rx burst size register (addr: 0x700) bit name description type 1 default register description: spi4-2 rx interface start-up parameters for burst size. 0x00060002 31 idles 1 = inserts four idle control words between each burst. (this occurs not only on an eop, but also at the end of every maxburst1 or maxburst2.) 0 = zero idle insertion between transfer bursts. r/w 0x0 30:25 reserved reserved ro 0x00 24:16 maxburst1 maximum number of 16-byte blocks that the fifo in the receive path, external to ixf1110, can accept when the fifo status channel indicates starving. r/w 0x006 15:9 reserved reserved ro 0x00 8:0 maxburst2 maximum number of 16-byte blocks that the fifo in the receive path, external to the ixf1110, can accept when the fifo status channel indicates hungry. r/w 0x002 1. ro = read only; rr = clear on read; w = write; r/w = read/write table 84. spi4-2 rx training register (addr: 0x701) bit name description type 1 default register description: spi4-2 rx interface start-up parameters for training sequences 0x00000000 31:24 reserved reserved ro 0x00 23:16 rep_t number of repetitions of the data training sequence that must be scheduled every data_max_t cycles r/w 0x00 15:0 data_max_t 2 maximum interval (in number of cycles) between scheduling of training sequences on receive data path interface an all zero value disables periodic training sequences. r/w 0x0000 1. ro = read only; rr = clear on read; w = write; r/w = read/write 2. the value of data_max_t is the most significant 16 bi ts of a 24-bit counter value. the least significant 8 bits are always 0x00. this allows for a much larger dat_max_t time-out period and provides a more than adequate granularity of selection.
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 141 document #: 250210 revision #: 004 rev. date: december 18, 2002 table 85. spi4-2 rx calendar register (addr: 0x702) bit name description type 1 default value register description: spi4-2 rx interface start-up parameters for fifo status calendar operation. 0x00010300 31:30 rx train test modes 00 = normal mode. 01 = do not enter training based on a repeating ?11? pattern on rstat[1:0] 1x = train continuously r/w 0x0 29 rsclk_invert 1 = the fifo status is captured on the falling edge of rsclk 0 = the fifo status is captured on the rising edge of the rsclk as per the spi4-2 specification. r/w 0 28 tsclk_invert 1 = the fifo status is launched on the falling edge of tsclk 0 = the fifo status is launched on the rising edge of the tsclk as per the spi4-2 specification. r/w 0 27:21 reserved reserved ro 0x000 20 dip2_error set based on an incorrect rx dip2 result. this bit is cleared upon a read rr 0x0 19:16 dip-2_thr defines how many consecutive correct dip- 2s are required to disable sending of training sequences on the rx spi4-2. r/w 0x1 15:14 reserved reserved ro 0x0 13 rx spi4 sync 1 = rx spi4 out of training (rdat = idles). 0 = rx spi4 in training (rdat = training). ro 0 12 tx spi4 sync 1 = the tx spi4-2 has received the valid training patterns on tdat and is now sending a 10 port calendar on tsat with valid fifo information. 0 = tx spi4-2 calendar is in constant framing. ro 0 11:8 loss_of_sync loss-of-sync is a parameter specifying the number of consecutive framing calendar cycles required to indicate a loss of synchronization and restart training sequences. r/w 0x3 7:4 reserved reserved ro 0x0 3:0 cal_m number of times fifo status for ports 0 through 9 repeat between framing and dip-2 cycles over the default value of 1. r/w 0x0 1. r0 = read only; rr = clear on read; w = write only; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 142 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 6.5.8 serdes register overview table 87 through table 89 on page 143 define the contents of the serdes register block at base location 0x780 which contain the control and status for the ten serdes interfaces on the ixf1110. table 86. spi4-2 tx synchronization register (addr: 0x703) bit name description type 1 default register description: spi4-2 synchronization dip-4 counters. 0x00000420 31:16 dip4_errors dip4_errors is the total number of dip4 errors detected since this register was last read. rr 0x0000 15:8 dip4_unlock 2 dip-4_unlock is a spi4-2 parameter specifying the number of incorrect dip4 fields to be detected to declare loss of synchronization and drive the tstat[1:0] bus with framing. r/w 0x04 7:0 dip4_lock number of consecutive correct dip4 results to achieve synchronization and end training r/w 0x20 1. ro = read only; rr = clear on read; w = write; r/w = read/write 2. when periodic training is enabled, the actual count of dip4 errors required to lose synchronization is 1 less than the programmed value in this register. therefore, this value should always be programmed to be 1 more than the desired value and should never be programmed to either 0 or 1. table 87. tx and rx ac/dc coupling selection register (addr: 0x780) bit name description type 1 default register description: allows selection of ac or dc coupling on the output of each serdes port (tx and rx are independent) 0x00000000 31:20 reserved reserved ro 0x000 19 rxacdc9 selects line coupling mode, ac = 0, dc = 1 r/w 0 18 txacdc9 selects line coupling mode, ac = 0, dc = 1 r/w 0 17 rxacdc8 selects line coupling mode, ac = 0, dc = 1 r/w 0 16 txacdc8 selects line coupling mode, ac = 0, dc = 1 r/w 0 15 rxacdc7 selects line coupling mode, ac = 0, dc = 1 r/w 0 14 txacdc7 selects line coupling mode, ac = 0, dc = 1 r/w 0 13 rxacdc6 selects line coupling mode, ac = 0, dc = 1 r/w 0 12 txacdc6 selects line coupling mode, ac = 0, dc = 1 r/w 0 11 rxacdc5 selects line coupling mode, ac = 0, dc = 1 r/w 0 10 txacdc5 selects line coupling mode, ac = 0, dc = 1 r/w 0 9 rxacdc4 selects line coupling mode, ac = 0, dc = 1 r/w 0 8 txacdc4 selects line coupling mode, ac = 0, dc = 1 r/w 0 7 rxacdc3 selects line coupling mode, ac = 0, dc = 1 r/w 0 6 txacdc3 selects line coupling mode, ac = 0, dc = 1 r/w 0 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 143 document #: 250210 revision #: 004 rev. date: december 18, 2002 5 rxacdc2 selects line coupling mode, ac = 0, dc = 1 r/w 0 4 txacdc2 selects line coupling mode, ac = 0, dc = 1 r/w 0 3 rxacdc1 selects line coupling mode, ac = 0, dc = 1 r/w 0 2 txacdc1 selects line coupling mode, ac = 0, dc = 1 r/w 0 1 rxacdc0 selects line coupling mode, ac = 0, dc = 1 r/w 0 0 txacdc0 selects line coupling mode, ac = 0, dc = 1 r/w 0 table 88. tx and rx power-down ports 0-9 register (addr: 0x787) bit name description type 1 default register description: tx and rx power-down bits to allow per-port power-down of unused ports 0x00000000 31:20 reserved reserved ro 0x000 19:10 tpwrdwn[9:0] tx power-down for ports 9-0 (1 = power-down) r/w 0000000000 9:0 rpwrdwn[9:0] rx power-down power-down for ports 9-0 (1 = power-down) r/w 0000000000 1. ro = read only; rr = clear on read; w = write; r/w = read/write table 89. rx signal detect level ports 0-9 register (addr: 0x793) bit name description type 1 default register description: this register shows the status of the rx input in relation to the level of the signal being received from the line, and is mainly used for debug and test purposes. 0x00000000 31:10 reserved reserved ro 0x000000 9 rx signal detect port 9 signal detect for port 9 0 = noise 1 = signal ro 0 8 rx signal detect port 8 signal detect for port 8 0 = noise 1 = signal ro 0 7 rx signal detect port 7 signal detect for port 7 0 = noise 1 = signal ro 0 6 rx signal detect port 6 signal detect for port 6 0 = noise 1 = signal ro 0 5 rx signal detect port 5 signal detect for port 5 0 = noise 1 = signal ro 0 1. ro = read only; rr = clear on read; w = write; r/w = read/write table 87. tx and rx ac/dc coupling selection register (addr: 0x780) (continued) bit name description type 1 default 1. ro = read only; rr = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 144 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 6.5.9 gbic block register overview table 90 through table 93 provide an overview of the gbic block registers. these registers provide a means to contro l and monitor the interf ace to the gbic modules. 4 rx signal detect port 4 signal detect for port 4 0 = noise 1 = signal ro 0 3 rx signal detect port 3 signal detect for port 3 0 = noise 1 = signal ro 0 2 rx signal detect port 2 signal detect for port 2 0 = noise 1 = signal ro 0 1 rx signal detect port 1 signal detect for port 1 0 = noise 1 = signal ro 0 0 rx signal detect port 0 signal detect for port 0 0 = noise 1 = signal ro 0 table 89. rx signal detect level ports 0-9 register (addr: 0x793) (continued) bit name description type 1 default 1. ro = read only; rr = clear on read; w = write; r/w = read/write table 90. gbic status register ports 0-9 (addr: 0x799) bit name description type 1 default register description: this register provides gbic status information. 0x00000000 31:30 reserved reserved ro 00 29:20 rx_los_9:0 rx_los inputs for ports 0-9 ro 0000000000 19:10 tx_fault_9:0 tx_fault inputs for ports 0-9 ro 0000000000 9:0 mod_def_9:0 mod_def inputs for ports 0-9 ro 0000000000 1. ro = read only; rr = clear on read; w = write only; r/w = read/write table 91. gbic control register ports 0-9 register (addr: 0x79a) bit name description type 1 default register description: this register provides access to gbic interrupt enables and tx_disable status information. 0x00000000 31:13 reserved reserved ro 0000000000 000000000 12 rx_los_en enable for rx_los_int operation (enabled = 1) r/w 0 1. ro = read only; rr = clear on read; w = write only; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 145 document #: 250210 revision #: 004 rev. date: december 18, 2002 11 tx_fault_en enable for tx_fault_int operation (enabled = 1) r/w 0 10 mod_def_en enable for mod_def_int operation (enabled = 1) r/w 0 9:0 tx_disable_9:0 tx_disable outputs for ports 0-9 r/w 0000000000 table 92. i 2 c control register ports 9-0 register (addr: 0x79b) bit name description type 1 default register description: this register controls i 2 c reads and writes. 0x00000000 31:29 reserved reserved ro 000 28 port address error port address error is set to 1 when an access is requested to port address > 0x9. ro 0 27 wp_err write protect error is set to 1 when a write access is requested to device id = 0xa and register address [10:8] = 0. this address combination is used solely for the read only gbic. ro 0 26 no_ack-err this bit is set to 1 when a gbic has failed to assert an acknowledge cycle. this signal should be used to validate the data being read. data is only valid if this bit is equal to zero. ro 0 25 i 2 cenable enables device wide i 2 c accesses (enabled = 1) r/w 0 24 i 2 c start i 2 c start = 1 will initiate the i 2 c cycle. this bit is clear on read. rr 0 23 reserved reserved ro 0 22 write complete write complete is set to a 1 when the byte write cycle has completed. ro 0 21 reserved reserved ro 0 20 read valid read valid is set to a 1 when valid data is available in the dataread7:0 field. ro 0 19:16 port address select 3:0 address of the ixf1110 port to be accessed r/w 0x0 15 read/write 1 = read, 0 = write. r/w 1 14:11 device id most significant 4 bits of device id/address field. r/w 0xa 10:0 register address bits 10:8 define least significant 3 bits of device id/ address field. bits 7:0 define the register address. r/w 00000000000 1. ro = read only; rr = clear on read; w = write only; r/w = read/write table 91. gbic control register ports 0-9 register (addr: 0x79a) bit name description type 1 default 1. ro = read only; rr = clear on read; w = write only; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 146 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 table 93. i 2 c data register ports 9-0 register (addr: 0x79c) bit name description type 1 default register description: this register provides i 2 c reads and writes. 0x00000000 31:24 reserved reserved ro 0x00 23:16 write data write_data contains the data to be written during the i 2 c byte write cycle. r/w 0x00 15:8 reserved reserved ro 0x00 7:0 read_data read_data contains the byte received during the last i 2 c read cycle. ro 0x00 1. ro = read only; rr = clear on read; w = write only; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 147 document #: 250210 revision #: 004 rev. date: december 18, 2002 7.0 package overview cbga packages are suited for applications requiring high i/o counts and high electrical performance. they are recommended for high-pow er applications, having high noise immunity requirements. 7.1 features ? flip chip die attach; surface mo unt second-level interconnect ? high electrical performance ? high i/o counts ? area array i/o options ? multiple power zone offering suppor ts core and four additional voltages ? jedec-compliant package 7.2 package specifics for the ixf1110 the ixf1110 uses the fo llowing packaging (see figure 43, ?ixf1110 552-ceramic ball grid array (cbga) package specification? on page 149 ): ? 552-ball cbga ? ball pitch of 1.0 mm ? overall package dimensions of 25 mm x 25 mm
intel ? ixf1110 10-port gigabit ethernet media access controller 148 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 7.2.1 markings character font size 0.04 - 0.10? 0.06 - 0.10? 25.0 mm 9.3 x 9.3 mm 25.0 mm pin 1 mark a aa000aaa = intel product number 0.19 - 0.24? ? 0.07 - 0.12? r note: * "pin 1 " does mean a pin1 indicator, not an actual mark. country x x = intel silicon revision number, a0, a1, b0 ? diameter of trademark circles are 70 mils substrate pn = substrate material number (barely visible) jjjjjjjj = manufacturing lot number syww9001 = intel finished process order (fpo) number country = assy plant country of origin topside fields not to scale diameter of pin 1 mark is 70 mils, and is located opposite the top-side substrate ?pin 1? identifier. qq = quality level, p: proto type, pq: pre-production, ? ?: production (no marking) ++ ++ = rework indicator syww9001 back of the die (bare silicon) substrate pn
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 149 document #: 250210 revision #: 004 rev. date: december 18, 2002 figure 43. ixf1110 552-ceramic ball grid array (cbga) package specification b0611-01 1 b 2 (25 0.2) (23) (25 0.2) (23) (23x) typ chip carrier a01 corner (23x) typ (0.91 max) (0.33 min) (reference) (0.91 max) (0.33 min) (575x) ( ? 0.8 0.05) (i/o pads) (reference) ? 0.20 da l s b s b0612-01 4.8 4.835 chip substrate 9.6 9.67 (25 0.2) (25 0.2) 47p6802 note: all dimensions are in mm.
intel ? ixf1110 10-port gigabit ethernet media access controller 150 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002 figure 44. ixf1110 cbga package side view diagram b0610-01 seating plane 0.15 c (4.237 max) (3.519 min) (3.327 max) (2.809 min) (2.47 max) (2.03 min) 0.81 0.1 (0.857 max) (0.779 min) chip c4 encapsulant fillet 45l4867 (552) solder ball note: all dimensions are in mm.
intel ? ixf1110 10-port gigabit ethernet media access controller preliminary datasheet 151 document #: 250210 revision #: 004 rev. date: december 18, 2002 8.0 product ordering information table 94. product information number revision qualification mm number ship media hfixf1110cc.a2 qe000 a2 q 848598 tray hf1110cc.a2 smpl qe000 a2 q 849909 tray figure 45. ordering information - sample temperature range a c e = ambient (0 - 55 c) = commercial (0 - 70 c) = extended (-40 - +85 c) product revision xn = 2 alphanumeric characters build format e000 e001 = tray = tape and reel hf q a1 c c 1110 ixf e000 internal package designator l p n q h t b c e k = lqfp = plcc = dip = pqfp = qfp with heat spreader = tqfp = bga = cbga = tbga = hsbga (bga with heat slug) qualification q s = pre-production material = production material ixa product prefix lxt ixe ixf ixp = phy layer device = switching engine = formatting device (mac) = network processor intel package designator dj fa fl fw hb hd hf hg s gc n = lqfp = tqfp = pbga (<1.0 mm pitch) = pbga (1.27 mm pitch) = qfp with heat spreader = qfp with heat slug = cbga = soic = qfp = tbga = plcc xxxx = 3-5 digit alphanumeric product code
intel ? ixf1110 10-port gigabit ethernet media access controller 152 preliminary datasheet document #: 250210 revision #: 004 rev. date: december 18, 2002

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